ST_DatapathCfg UHD60_R10_YUV422_8_CFG = {
  //DATAPLL
  2,                   //NMP rxpix_clk:0,1621,2972,324
  0,                   //NVC1 video_clk1:0,297mhz1,148.5mhz2,13.5mhz
  0x3F,                //NVC2_S1
  0,                   //NVC2_S2 video_clk2:0x3f0,2970x3f1,1480x3f4,74.25
  //Regs of MIPI-RX
  0x2,                 //MODE_P0_OPERATION
  0x2,                 //PHYA_RX_MODE
  0x1,                 //MODE_P0_PIX_PARA
  0x3,                 //DPHY_P0_MODE_LANENUM 4 lane MODE
  0x0,                 //DPHY_P0_LP_SYNC_OFF
  0x0,                 //DPHY_P0_MODE_HSDM_OFF
  0x1,                 //DPHY_P0_MODE_MSB_FIRST
  0x0,                 //DPHY_P0_MODE_LPOP_OFF
  0,                   //DPHY_P0_TIME_HS_ON
  0x20,                //DPHY_P0_TIME_RES_ON imx415 891 mpbs 0x0d~0x26 is ok
  0x1,                 //APP_P0_CHK_VENA
  0x1,                 //APP_P0_CHK_HENA
  2250,                //APP_P0_CHK_VSIZE
  3864,
  1,
  1,
  1,
  1,
  1,
  1,
  1,
  1,
  1,
  1,
  1,
  1,
  //Regs of CCHG
  2250,
  4400,
  2229, //   NUM_ROL
  3864, //   NUM_COL
  100,
  //Regs of ISP
  3864,
  2176,
  3,
  0,
  0, // For 10bits mode {raw-10 --> yuv-8}
  0xc0,                //OB_R_SUB
  0xc0,                //OB_GR_SUB
  0xc0,                //OB_GB_SUB
  0xc0,                //OB_B_SUB
  64,
  2200,//1464
  2000,//1464
  0,
  0,
  4, // ES2 needs to be modified
  4, // ES2 needs to be modified
  64,
  0,
  0,
  64,
  64,
  0,
  128,
  96,
  40,
  22,
  2/2,
  51,
  8,
  8,
  44,
  10,
  4400/2,
  2250,
  3840/2,
  2160,
  384/2,
  82,
  //Regs of LISR
  1,                   //input on/off
  1,                   //00/01/10/11->RGB/YUV422/YUV444/RESVE
  1,                   //IN_FRATE 000/001/010/011/100/111->30/60/120/240/59.9401/else fps
  3840,                //IN_HSIZE
  2160,                //IN_VSIZE
  1,                   //INH_SD
  0,                   //SD_MODE
  3840,                //SD_HSIZE
  2160,                //SD_VSIZE
  11,                  //OUT_RESO
  1,                   //OUT_FRATE 000/001/010/011/100/111->30/60/120/240/59.9401/else fps
  0,                   //OUT_I_P
  9,                   //AHE_BLKSIZ
  0,                   //CROP_HOFF
  0,                   //CROP_VOFF
  0,                   //AHE_ON
  1,                   //VIDEO_ON
  1,                   //OUT_FORM // 0:RGB888 1:YUV422_8 5:YUV422_10
  0,                   //OUT_THRU
  1,                   //OUT_DISP_ON
  3840,                //AHE_HWIDTH
  2160,                //AHE_VWIDTH
  1,                   //AHEF_ON
  1,                   //UVENHON
  3,                   //MOVESW
  255,                 //ALPHA_AHE
  // Regs of MIPI_TX
  19,                  //DPHY_P0_TX_TIME_T_LPX
  14,                  //DPHY_P0_TX_TIME_T_CLK_PREPARE
  99,                  //DPHY_P0_TX_TIME_T_CLK_ZERO
  0,                   //DPHY_P0_TX_TIME_T_CLK_PRE
  19,                  //DPHY_P0_TX_TIME_T_HS_PREPARE
  40,                  //DPHY_P0_TX_TIME_T_HS_ZERO
  0,                   //DPHY_P0_TX_TIME_T_HS_SOT
  19,                  //DPHY_P0_TX_TIME_T_HS_EOT
  2,                   //DPHY_P0_TX_TIME_T_CLK_POST
  19,                  //DPHY_P0_TX_TIME_T_CLK_EOT
  400,                 //DPHY_P0_TX_TIME_T_WAKEUP
  3,                   //DPHY_P0_TX_LP11
  2,                   //DPHY_P0_TX_LP10
  1,                   //DPHY_P0_TX_LP01
  0,                   //DPHY_P0_TX_LP00
  0,                   //CSI2_P0_TX_TC
  0,                   //CSI2_P0_TX_TS
  3,                   //MODE_LANENUM
  0,                   //PHYA_PLL_PDIV Input reference clock divider: Divider ratio  (PDIV + 1)
  0,                   //PHYA_PLL_N1DIV High Speed Feedback clock divider: Divider ratio: 1/2/4/8
  87,                  //PHYA_PLL_N2DIV Feedback clock divider: Divider ratio  (N2DIV + 1)
  0,                   //PHYA_PLL_K1DIV Output clock divider for CLK_P/N_O : Divider ratio : 1/2/4/8
  0,                   //PHYA_PLL_K2DIV Output clock divider-1 for LS_CLK_O : Divider ratio : 1/2/4/8
  7,                   //PHYA_PLL_K3DIV Output clock divider-2 for LS_CLK_O : Divider ratio  (K3DIV + 1)
};
