//sensor HMAX   :
//rx serial-rate:891mbps
//rx pix_clk    :162mhz
//video_clk1    :148.5mhz
//video_clk2    :74.25mhz
//tx serial-rate:1188mbps

#define D_HMAX                           0x226//60fps

#define D_NMP                            0      //rx pix_clk: 0,162 1,297 2,324
#define D_NVC1                           1      //video_clk1: 0,297mhz 1,148.5mhz 2,13.5mhz
#define D_NVC2_S1                        0x3F
#define D_NVC2_S2                        0x04   //video_clk2: 0x3f 0,297 0x3f 1,148 0x3f 4,74.25

//FHD60_YUV422_8
#define img_in_h_size                    4400
#define img_in_v_size                    1125
#define img_in_h_vld_size                1932
//#define img_in_v_vld_size   1096 + 2
#define img_in_v_vld_size                1116   // 1117 instead of 1116, due to CCHG update, 2023-07-11.
// 1117 doesn't work, return to 1116. @2023-07-14

//Regs of MIPI-RX
#define D_MODE_P0_OPERATION              0x2
#define D_PHYA_RX_MODE                   0x2
#define D_MODE_P0_PIX_PARA               0x1
#define D_DPHY_P0_MODE_LANENUM           0x3 // 4 lane MODE
#define D_DPHY_P0_LP_SYNC_OFF            0x0
#define D_DPHY_P0_MODE_HSDM_OFF          0x0
#define D_DPHY_P0_MODE_MSB_FIRST         0x1 // 1'h0 NG(?)
#define D_DPHY_P0_MODE_LPOP_OFF          0x0

#define D_DPHY_P0_TIME_HS_ON             0
//#define D_DPHY_P0_TIME_RES_ON     0x0020 // for os05a20 742.5 mbps 0x11~0x37 is ok
#define D_DPHY_P0_TIME_RES_ON            0x20 // for imx415 891 mpbs 0x0d~0x26 is ok

#define D_APP_P0_CHK_VENA                0x1
#define D_APP_P0_CHK_HENA                0x1
#define D_APP_P0_CHK_VSIZE               img_in_v_vld_size
#define D_APP_P0_CHK_HSIZE               1944
#define D_LINK_P0_RST_N                  1
#define D_PHYA_RX_IREF_POW_EN            1
#define D_PHYA_RX_D0_HS_AMP_POW_EN       1
#define D_PHYA_RX_D1_HS_AMP_POW_EN       1
#define D_PHYA_RX_D2_HS_AMP_POW_EN       1
#define D_PHYA_RX_D3_HS_AMP_POW_EN       1
#define D_PHYA_RX_C0_HS_AMP_POW_EN       1
#define D_PHYA_RX_D0_LP_AMP_POW_EN       1
#define D_PHYA_RX_D1_LP_AMP_POW_EN       1
#define D_PHYA_RX_D2_LP_AMP_POW_EN       1
#define D_PHYA_RX_D3_LP_AMP_POW_EN       1
#define D_PHYA_RX_C0_LP_AMP_POW_EN       1

//Regs of CCHG
#define D_CCHG_V_SIZE                    img_in_v_size
#define D_CCHG_H_SIZE                    img_in_h_size
#define D_V_VALID_SIZE                   img_in_v_vld_size //   NUM_ROL
#define D_H_VALID_SIZE                   img_in_h_vld_size //   NUM_COL
#define D_BANK_CYCLE                     100
//Regs of ISP
#define D_NUM_COL                        img_in_h_vld_size
#define D_NUM_ROW                        1088
#define D_BAYER_PATTERN                  3
#define D_THROUGH_MODE                   0
#define D_BIT_MODE                       1 // For 10bits mode {raw-12 --> yuv-10}
#define D_OB_R_SUB                       0
#define D_OB_GR_SUB                      0
#define D_OB_GB_SUB                      0
#define D_OB_B_SUB                       0
#define D_TOTAL_GAIN                     64
#define D_WB_R_GAIN                      2155//1464
#define D_WB_B_GAIN                      1805//1464
#define D_GAMMA_FACTOR                   0
#define D_APERTURE_TH                    0
#define D_APERTURE_H                     4 // ES2 needs to be modified
#define D_APERTURE_V                     4 // ES2 needs to be modified
#define D_MATRIX_R_Y_G1                  64
#define D_MATRIX_R_Y_G2                  0
#define D_MATRIX_B_Y_G1                  0
#define D_MATRIX_B_Y_G2                  64
#define D_Y_OUT_GAIN                     64
#define D_Y_OUT_OFFSET                   0
#define D_PSEUDO_SUPPRESS                128
#define D_AE_AWB_UNIT                    48
#define D_AE_AWB_COL                     40
#define D_AE_AWB_ROW                     22
#define D_H_IN_OFFSET                    2/2
#define D_V_IN_OFFSET                    27
#define D_H_OUT_OFFSET                   6
#define D_V_OUT_OFFSET                   4
#define D_HS_WIDTH                       22
#define D_VS_WIDTH                       5
#define D_H_SIZE                         img_in_h_size/2
#define D_V_SIZE                         img_in_v_size
#define D_H_OUT_SIZE                     1920/2
#define D_V_OUT_SIZE                     1080
#define D_H_FR_BLK                       192/2
#define D_V_FR_BLK                       41

//Regs of LISR
#define D_IN_SEL                         1              //input on/off
#define D_IN_FORM                        1              //00/01/10/11->RGB/YUV422/YUV444/RESVE
#define D_IN_FRATE                       1              //000/001/010/011/100/111->30/60/120/240/59.9401/else fps
#define D_IN_HSIZE                       1920
#define D_IN_VSIZE                       1080

#define D_INH_SD                         0
#define D_SD_MODE                        0
#define D_SD_HSIZE                       1920
#define D_SD_VSIZE                       1080

#define D_OUT_RESO                       8
#define D_OUT_FRATE                      1
#define D_OUT_I_P                        0
#define D_AHE_BLKSIZ                     8
#define D_CROP_HOFF                      0
#define D_CROP_VOFF                      0

#define D_AHE_ON                         1
#define D_VIDEO_ON                       1
#define D_OUT_FORM                       1           // 0:RGB888 1:YUV422_8 5:YUV422_10
#define D_OUT_THRU                       0
#define D_OUT_DISP_ON                    1

#define D_AHE_HWIDTH                     1920
#define D_AHE_VWIDTH                     1080

#define D_AHEF_ON                        1
#define D_UVENHON                        1
#define D_MOVESW                         2

#define D_ALPHA_AHE                      255

// Regs of MIPI_TX
#define D_DPHY_P0_TX_TIME_T_LPX          20
#define D_DPHY_P0_TX_TIME_T_CLK_PREPARE  10
#define D_DPHY_P0_TX_TIME_T_CLK_ZERO     80
#define D_DPHY_P0_TX_TIME_T_CLK_PRE      0
#define D_DPHY_P0_TX_TIME_T_HS_PREPARE   12
#define D_DPHY_P0_TX_TIME_T_HS_ZERO      30
#define D_DPHY_P0_TX_TIME_T_HS_SOT       0
#define D_DPHY_P0_TX_TIME_T_HS_EOT       15
#define D_DPHY_P0_TX_TIME_T_CLK_POST     0
#define D_DPHY_P0_TX_TIME_T_CLK_EOT      15
#define D_DPHY_P0_TX_TIME_T_WAKEUP       400
#define D_DPHY_P0_TX_LP11                3
#define D_DPHY_P0_TX_LP10                2
#define D_DPHY_P0_TX_LP01                1
#define D_DPHY_P0_TX_LP00                0
#define D_CSI2_P0_TX_TC                  0
#define D_CSI2_P0_TX_TS                  0
#define D_MODE_LANENUM                   3
#define D_PHYA_PLL_PDIV                  0 // Input reference clock divider: Divider ratio  (PDIV + 1)
#define D_PHYA_PLL_N1DIV                 0 // High Speed Feedback clock divider: Divider ratio: 1/2/4/8
#define D_PHYA_PLL_N2DIV                 43 // Feedback clock divider: Divider ratio  (N2DIV + 1)
#define D_PHYA_PLL_K1DIV                 0 // Output clock divider for CLK_P/N_O : Divider ratio : 1/2/4/8
#define D_PHYA_PLL_K2DIV                 0 // Output clock divider-1 for LS_CLK_O : Divider ratio : 1/2/4/8
#define D_PHYA_PLL_K3DIV                 7 // Output clock divider-2 for LS_CLK_O : Divider ratio  (K3DIV + 1)

