ST_DatapathCfg FHD60_R12_YUV422_8_CFG = {
  //DATAPLL
  0,                   //NMP rxpix_clk:0,1621,2972,324
  1,                   //NVC1 video_clk1:0,297mhz1,148.5mhz2,13.5mhz
  0x3F,                //NVC2_S1
  4,                   //NVC2_S2 video_clk2:0x3f0,2970x3f1,1480x3f4,74.25
  //RegsofMIPI-RX
  0x2,                 //MODE_P0_OPERATION
  0x2,                 //PHYA_RX_MODE
  0x1,                 //MODE_P0_PIX_PARA
  0x3,                 //DPHY_P0_MODE_LANENUM 4 lane MODE
  0x0,                 //DPHY_P0_LP_SYNC_OFF
  0x0,                 //DPHY_P0_MODE_HSDM_OFF
  0x1,                 //DPHY_P0_MODE_MSB_FIRST
  0x0,                 //DPHY_P0_MODE_LPOP_OFF
  0,                   //DPHY_P0_TIME_HS_ON
  0x20,                //DPHY_P0_TIME_RES_ON
  0x1,                 //APP_P0_CHK_VENA
  0x1,                 //APP_P0_CHK_HENA
  1116,                //APP_P0_CHK_VSIZE
  1944,                //APP_P0_CHK_HSIZE
  1,                   //LINK_P0_RST_N
  1,                   //PHYA_RX_IREF_POW_EN
  1,                   //PHYA_RX_D0_HS_AMP_POW_EN
  1,                   //PHYA_RX_D1_HS_AMP_POW_EN
  1,                   //PHYA_RX_D2_HS_AMP_POW_EN
  1,                   //PHYA_RX_D3_HS_AMP_POW_EN
  1,                   //PHYA_RX_C0_HS_AMP_POW_EN
  1,                   //PHYA_RX_D0_LP_AMP_POW_EN
  1,                   //PHYA_RX_D1_LP_AMP_POW_EN
  1,                   //PHYA_RX_D2_LP_AMP_POW_EN
  1,                   //PHYA_RX_D3_LP_AMP_POW_EN
  1,                   //PHYA_RX_C0_LP_AMP_POW_EN
  //Regs of CCHG
  1125,                //CCHG_V_SIZE
  4400,                //CCHG_H_SIZE
  1116,                //V_VALID_SIZE NUM_ROL
  1932,                //H_VALID_SIZE NUM_COL
  100,                 //BANK_CYCLE
  //RegsofISP
  1932,                //NUM_COLi
  1088,                //NUM_ROW
  3,                   //BAYER_PATTERN
  0,                   //THROUGH_MODE
  1,                   //BIT_MODE 0:10bit,1:12bit
  0xc0,                //OB_R_SUB
  0xc0,                //OB_GR_SUB
  0xc0,                //OB_GB_SUB
  0xc0,                //OB_B_SUB
  64,                  //TOTAL_GAIN
  2200,                //WB_R_GAIN
  2000,                //WB_B_GAIN
  0,                   //GAMMA_FACTOR
  0,                   //APERTURE_TH
  4,                   //APERTURE_H ES2 needs to be modified
  4,                   //APERTURE_V ES2 needs to be modified
  64,                  //MATRIX_R_Y_G1
  0,                   //MATRIX_R_Y_G2
  0,                   //MATRIX_B_Y_G1
  64,                  //MATRIX_B_Y_G2
  64,                  //Y_OUT_GAIN
  0,                   //Y_OUT_OFFSET
  128,                 //PSEUDO_SUPPRESS
  48,                  //AE_AWB_UNIT
  40,                  //AE_AWB_COL
  22,                  //D_AE_AWB_COL
  2/2,                 //D_AE_AWB_ROW
  27,                  //V_IN_OFFSET
  6,                   //H_OUT_OFFSET
  4,                   //V_OUT_OFFSET
  22,                  //HS_WIDTH
  5,                   //VS_WIDTH
  4400/2,              //H_SIZE
  1125,                //V_SIZE
  1920/2,              //H_OUT_SIZE
  1080,                //V_OUT_SIZE
  192/2,               //H_FR_BLK
  41,                  //V_FR_BLK
  //RegsofLISR
  1,                   //IN_SEL input on/off
  1,                   //IN_FORM 00/01/10/11->RGB/YUV422/YUV444/RESVE
  1,                   //IN_FRATE 000/001/010/011/100/111->30/60/120/240/59.9401/else fps
  1920,                //IN_HSIZE
  1080,                //IN_VSIZE
  0,                   //INH_SD
  0,                   //SD_MODE
  1920,                //SD_HSIZE
  1080,                //SD_VSIZE
  8,                   //OUT_RESO
  1,                   //OUT_FRATE
  0,                   //OUT_I_P
  8,                   //AHE_BLKSIZ
  0,                   //CROP_HOFF
  0,                   //CROP_VOFF
  0,                   //AHE_ON
  1,                   //VIDEO_ON
  1,                   //OUT_FORM // 0:RGB888 1:YUV422_8 5:YUV422_10
  0,                   //OUT_THRU
  1,                   //OUT_DISP_ON
  1920,                //AHE_HWIDTH
  1080,                //AHE_VWIDTH
  1,                   //AHEF_ON
  1,                   //UVENHON
  2,                   //MOVESW
  255,                 //ALPHA_AHE
  // Regs of MIPI_TX
  20,                  //DPHY_P0_TX_TIME_T_LPX
  10,                  //DPHY_P0_TX_TIME_T_CLK_PREPARE
  80,                  //DPHY_P0_TX_TIME_T_CLK_ZERO
  0,                   //DPHY_P0_TX_TIME_T_CLK_PRE
  12,                  //DPHY_P0_TX_TIME_T_HS_PREPARE
  30,                  //DPHY_P0_TX_TIME_T_HS_ZERO
  0,                   //DPHY_P0_TX_TIME_T_HS_SOT
  15,                  //DPHY_P0_TX_TIME_T_HS_EOT
  0,                   //DPHY_P0_TX_TIME_T_CLK_POST
  15,                  //DPHY_P0_TX_TIME_T_CLK_EOT
  400,                 //DPHY_P0_TX_TIME_T_WAKEUP
  3,                   //DPHY_P0_TX_LP11
  2,                   //DPHY_P0_TX_LP10
  1,                   //DPHY_P0_TX_LP01
  0,                   //DPHY_P0_TX_LP00
  0,                   //CSI2_P0_TX_TC
  0,                   //CSI2_P0_TX_TS
  3,                   //MODE_LANENUM
  0,                   //PHYA_PLL_PDIV Input reference clock divider: Divider ratio  (PDIV + 1)
  0,                   //PHYA_PLL_N1DIV High Speed Feedback clock divider: Divider ratio: 1/2/4/8
  43,                  //PHYA_PLL_N2DIV Feedback clock divider: Divider ratio  (N2DIV + 1)
  0,                   //PHYA_PLL_K1DIV Output clock divider for CLK_P/N_O : Divider ratio : 1/2/4/8
  0,                   //PHYA_PLL_K2DIV Output clock divider-1 for LS_CLK_O : Divider ratio : 1/2/4/8
  7,                   //PHYA_PLL_K3DIV Output clock divider-2 for LS_CLK_O : Divider ratio  (K3DIV + 1)
};
