#ifndef DDR_FILE_H
#define DDR_FILE_H




struct predefine{
int NANYA;


int DDR2;
int DDR3;
int DDR4;

int LPDDR2;
int LPDDR3;
int LPDDR4;
int LPDDR4X;

int COMMAND_TRAIN ;
int WRITE_LEVELING ;
int DQS_CALIB ;
int RD_TRAIN ;
int WR_TRAIN ;

int DDR2_800 ;
int DDR2_1066;
int LPDDR2_800;
int LPDDR2_1066;
int LPDDR2_666;


int DDR3_800 ;
int DDR3_1066;
int DDR3_1333;
int DDR3_1600;
int DDR3_1866;
int DDR3_2133;

int LPDDR3_800 ;
int LPDDR3_1066;
int LPDDR3_1333;
int LPDDR3_1600;
int LPDDR3_1866;
int LPDDR3_2133;

int DDR4_800 ;  
int DDR4_1333;
int DDR4_1600;
int DDR4_1866;
int DDR4_2133;
int DDR4_2400;
int DDR4_2666;
int DDR4_3200;

int LPDDR4_800 ;
int LPDDR4_1600;
int LPDDR4_1866;
int LPDDR4_2133;
int LPDDR4_2400;
int LPDDR4_2666;
int LPDDR4_3200;
int LPDDR4_3733;
int LPDDR4_4266;

int DDR4_RDBI;
int DDR4_WDBI;
int DDR4_DBI;

int DQ8_H ;

int DQ8 ;
int DQ16 ;
int DQ16_H ;
int DQ24 ;
int DQ32 ;
int DQ40 ;
int DQ48 ;
int DQ56 ;
int DQ64 ;
int DQ72 ;
int DQ8_1 ;
int DQ8_2 ;
int DQ8_3 ;


int DQ ;
int VREF ;
int BURST8 ;
int NORMAL_INIT ;

int tINIT3_LPDDR2 ;
int tINIT5_LPDDR2 ;
int tZQINIT_LPDDR2 ;
int tINIT1_LPDDR4 ;
int tINIT3_LPDDR4 ;
int tINIT5_LPDDR4 ;
int tINIT3_LPDDR3 ;
int tINIT5_LPDDR3 ;
int tZQINIT_LPDDR3 ;
int tRESET_DDR3 ;
int tCKE_DDR3 ;
int tZQINIT_DDR3 ;
int tPW_RESET_L_DDR4 ;
int tCKE_DDR4 ;
int tZQINIT_DDR4 ;

int DLL;
int DQS_CALIB_AUTO_REF;
int ZQCALIB_TYPE_SEL;
int WR_TRAIN_UI_EXPAND;
int SPECIAL_RANK_SIGNAL;
int FOUR_FREQ;
int RTRAIN;
int LPB_CKE_0_CLKEN_CKE_0;
int CORE_RSTN_CHECK ;
int DQS_DEFAULT_CHECK ;
//int cmd_perbit_skew_offset ;
int FREQ_NUM  ;
//int RANK_NUM  ;
int BYTE_NUM  ;
int DQ_LANE  ;
int RANK1;
int RANK2;
int RANK4;
int RANK2_OR_RANK4;
int ck_invdelay;
int wl_dqs_default_dly;
int IO_MAP;
int IO_DELAY;
int DM_SCAN;
int LPDDR3_OR_LPDDR2;
int DDR3_OR_DDR2;


int CK_RATIO_CAL;
float CK_PERIOD;
int SPEED_GRADE;
int SPEED_800;
int SPEED_1066;
int SPEED_1333;
int SPEED_1600;
int SPEED_1866;
int SPEED_2133;
int SPEED_2400;
int SPEED_2666;
int SPEED_2750;
int SPEED_2933;
int SPEED_3200;
int SPEED_3733;
int SPEED_4000;
int SPEED_4266;
int MIX_SIM;

int DQ_LANE1;
int DQ_LANE2;
int DQ_LANE3;
int DQ_LANE4;
int DQ_LANE5;
int DQ_LANE6;
int DQ_LANE7;
int DQ_LANE8;
int DQ_LANE9;

int CMD_2T;
int ONE_UI;
//int CTRL_SIM;
int WDQS_CTRL_MODE1;
int CG_DIS;
int ZQCALI;


int WRITE_LEVELING_ERROR;
int DQS_CALIB_ERROR;
int RD_TRAIN_ERROR;
int WR_TRAIN_ERROR;
int WT_VREF_EN;
int MPR_RD_CALIB;
int ZQCALIB_CLEAR;

int E203_EN;


int cmd_drv_nr;
int cmd_drv_pr;
int dq_dqs_drv_nr;
int dq_dqs_drv_pr;
int ck_drv_nr;
int ck_drv_pr;

int dq_odt_pu;
int dq_odt_pd;

int dq_vref;

////ctrl///

int BURST16;
int BURST_16;
int BURST_32;
int AUTO_REF_BURST;
int ECC_EN;
int AUTO_PRE;
int APB_RANDOM;
int PRI_RAND;
int ADDR_MODE0;
int ADDR_MODE1;
int ADDR_MODE2;
int ADDR_MODE3;
int ADDR_MODE4; 
int OUT_OF_ORDER;
int CWL_CL_AL_BP;
int MAX_LIMI;
int TIMING_DEBUG;

int LPDDR4_WL_B;
int RDBI_EN;
int WDBI_EN;
int DDR_BANK_DEFINE;
int DDR_ROW_DEFINE;
int DDR_COL_DEFINE;
int LPDDR2_1200;
int FREQ_CHANGE;
};

struct apb_transaction
{
    int             ddr3_bl;
    int                ddr3_cl;
    int                ddr3_wr;
    int               ddr3_cwl;
    int                ddr3_al;
    int             ddr2_bl;
    int                ddr2_cl;
    int                ddr2_al;
    int                ddr2_wr;

    int          lpddr2_bl;
    int          lpddr2_rl_wl;
    int          lpddr2_wr;  

    int          lpddr3_bl;
    int          lpddr3_rl_wl;
    int          lpddr3_wr;     
        //ddr4
    int             ddr4_bl;
    int                ddr4_cl;
    int               ddr4_cwl;
    int                ddr4_al;
    int            ddr4_wr_rtp;
    int            ddr4_tccd_l;
    int		ddr4_rd_dbi;
        //lpddr4
    int           lpddr4_bl;
    int              lpddr4_wr;
    int          lpddr4_rl_rtp;
    int              lpddr4_wl;
    int     lpddr4_rd_preamble;
    int             lpddr4_wls;
    int           lpddr4_rldbi;

    int		                  trefi;
    int		                   trfc;

    int		                   tvrefca_long;
    int		                   tdstrain;

    int             phy_bl;
    int		               phy_cl;
    int		               phy_al;
    int		               phy_cwl;

    int		               pllfbdiv;
    int		               pllprediv;
    int         phy_mem;
    int		               phy_channel_en;
    int                        ddr4_wr_dbi;
 
    int         speed_grade;
    int         pllfbdiv_offset;
    float       ck_offset;
    float       pllfbdiv_before_offset;
    float       pllfbdiv_after_offset;
    float       trefi_real;
    float       trfc_real;
    int   trefi_int;
    int    trfc_int;


////////ctrl///////////////////////////////

    int        sdram_dq_width;
    int     sdram_burst_length;
    int      phy_burst;
//    int        phy_mem;
    int       ddrc_mem_choose;
    int		          derated_trcd;
    int		          derated_trc;
    int		          derated_tras_min;
    int		          derated_trp;
    int		          derated_trrd_s;
    int		          derated_trrd_l;

    int		          trcd;
    int		          trc;
    int		          tras_min;
    int		          trp;
    int		           trtp;
    int		           twr;
    int		           trtw;
    int		           ddrc_rd2wr_of_diff_rank;    //UPDATE
    int		           twtr_s;
    int		           twtr_l;
    int		           twtpwd;
    int		           trtpwd;
    int		           tccd_s;
    int		           tccd_l;
    int		           tccd_mw;
    int		          trrd_s;
    int		          trrd_l;
    int		           tfaw;
    int		           tppd;
    int		          ddrc_txs;
    int		           ddrc_txp;
    int		           tpd;    //UPDATE
    int		          ddrc_tzqoper;
    int		           mrwreset_1us_x32;    //x32
    int		           lpddr23_tinit5_x32;    //x32
//    int		                   trfc;
//    int		                  trefi;
    int		           ddrc_init_treset_l_x1024   ;
    int		          ddrc_init_treset_h_x1024   ;
    int		           ddrc_trfc_min;
    int		           ddrc_tmrd             ;
    int		           ddrc_tmrw             ;
    int		           ddrc_tmod             ;
    int		           ddrc_tmrr             ;
    int		           ddrc_tmrr2mrw         ;
    int		           ddrc_trpa             ;
    int		           ddrc_trp              ;
    int		          ddrc_txpr             ;
    int		          ddrc_init_tzqinit          ;
    int		           ddrc_init_tzqlat           ;
    int		           ddrc_tdllk            ;
    int		           ddrc_trefi_x32       ;
    int		           ddrc_init_tckeh            ;
    int		           tinit1_100ns; 

//    int		           pllfbdiv;   //UPDATE
//    int		           pllprediv;  //UPDATE

//    int		                   tvrefca_long;
//    int		                   tdstrain;

    //bypass mode.
    int		           cl_bp;
    int		           cwl_bp; //UPDATE
    int		           al_bp;

    int		           bit_sel;
    int		           bist_mode_sel;
    int		           bist_addr_pattern_sel;
    int		           bist_data_pattern_sel;
    int		          bist_start_addr;
    int		          bist_end_addr;
    int		          bist_start_col;
    int		          bist_start_row;
    int		           bist_start_bank;
    int		           bist_start_rank;    //UPDATE

    int		          bist_end_col;
    int		          bist_end_row;
    int		           bist_end_bank;
    int		           bist_end_rank;  //UPDATE
    int		          bist_data;
    int		           mem_bist_channel_en;

//    int		           phy_cl;
//    int		           phy_cwl;    //UPDATE
//    int		           phy_al;     //UPDATE
    int		           sdram_col_size;
    int		           sdram_row_size;
    int		           sdram_bank_size;
    int		           sdram_bg_size;
    int		sdram_rank_size;

    //lpddr2
//    int      lpddr2_bl;
//    int      lpddr2_rl_wl;
//    int         lpddr2_wr;     
    //lpddr3
//    int      lpddr3_bl;
//    int      lpddr3_rl_wl;
//    int         lpddr3_wr;    
    //ddr3
//    int         ddr3_bl;
//    int            ddr3_cl;
//    int           ddr3_cwl;
//    int            ddr3_al;
//    int            ddr3_wr;    
    //ddr2
//    int         ddr2_bl;
//    int            ddr2_cl;
//    int            ddr2_al;
//    int            ddr2_wr;
    
    //ddr4
//    int             ddr4_bl;
//    int                ddr4_cl;
//    int               ddr4_cwl;
//    int                ddr4_al;
//    int            ddr4_wr_rtp;
//    int            ddr4_tccd_l;
    int		rdbi_en;
    int		wdbi_en;
    //int		ddr4_rdbi_en;
    //int		ddr4_rd_dbi;
    //int		ddr4_wr_dbi;
    
    
        //lpddr4
//    int           lpddr4_bl;
//    int              lpddr4_wr;
//    int          lpddr4_rl_rtp;
//    int              lpddr4_wl;
//    int     lpddr4_rd_preamble;
//    int             lpddr4_wls;


//    int		                   phy_channel_en;

    int		                  inno_ddr_phy_trefi;
    int		                   inno_ddr_phy_trfc;
    int		                   lpddr23_tinit5;
    int                             display_flag;


    int		ddrc_auto_ref_mode;  
    int		                       ddrc_auto_ref_burst;  
    int		                       lp_rqueue_max_dep;
    int		                       wqueue_max_dep;
    int		                       ddrc_wr_gap_of_diff_rank;
    int		                       ddrc_rd_gap_of_diff_rank;
    int		                      tras;  //
    int		                       tckesr;  //
    int		                       tcke;  //UPDATE
    int		                       wr_starve_time;
    int		                       rd_starve_time;
    int		                       rd2wr_switch_threhold;
    int		                       wr2rd_switch_threhold;
    int		                       ddrc_sref2dfilp_gap;
    int		                       ddrc_dfilp2sref_gap;
    int		                       ddrc_pd2dfilp_gap;
    int		                       ddrc_dfilp2pd_gap;
    int		prefer_write;
    int		pagematch_limit;
    int		                       wr_priority0;
    int		                       wr_priority1;
    int		                       wr_priority2;
    int		                       wr_priority3;
    int		                       wr_priority4;
    int		                       rd_port_priority0;
    int		                       rd_port_priority1;
    int		                       rd_port_priority2;
    int		                       rd_port_priority3;
    int		                       rd_port_priority4;
    int		wr_port_aging_en0;
    int		wr_port_aging_en1;
    int		wr_port_aging_en2;
    int		wr_port_aging_en3;
    int		wr_port_aging_en4;
    int		rd_port_aging_en0;
    int		rd_port_aging_en1;
    int		rd_port_aging_en2;
    int		rd_port_aging_en3;
    int		rd_port_aging_en4;
    int		pageclose_en;
    int		                       pageclose_timer;
    int		                       sdram_addr_map_mode;
    int		ddrc_2t_mode;
    int		ddrc_ecc_en;
    int		ddrc_ecc_dis_scrub;
    int		out_of_order_dis;
    int		cwl_al_cl_bp;
    int		                       dfi_lp_entry_wait_time;
    int		                       dfi_lp_wakeup_sref;
    int		                       dfi_lp_wakeup_pd  ;
    int		lpddr4_self_ppd_en  ;
    int		                       ddrc_tescke  ;

    int    lpddr4_load_mode13_fsp0 ;
    int    lpddr4_load_mode01_fsp0 ;
    int    lpddr4_load_mode02_fsp0 ;
    int    lpddr4_load_mode03_fsp0 ;
    int    lpddr4_load_mode11_fsp0 ;
    int    lpddr4_load_mode22_fsp0 ;
    int    lpddr4_load_mode12_fsp0 ;
    int    lpddr4_load_mode14_fsp0 ;
    int    lpddr4_load_mode13_fsp1 ;
    int    lpddr4_load_mode01_fsp1 ;
    int    lpddr4_load_mode02_fsp1 ;
    int    lpddr4_load_mode03_fsp1 ;
    int    lpddr4_load_mode11_fsp1 ;
    int    lpddr4_load_mode22_fsp1 ;
    int    lpddr4_load_mode12_fsp1 ;
    int    lpddr4_load_mode14_fsp1 ;

    int		                r_reg_ddrc_col_offset_bit0        ;
    int		                r_reg_ddrc_col_offset_bit1        ;
    int		                r_reg_ddrc_col_offset_bit2        ;
    int		                r_reg_ddrc_col_offset_bit3        ;
    int		                r_reg_ddrc_col_offset_bit4        ;
    int		                r_reg_ddrc_col_offset_bit5        ;
    int		                r_reg_ddrc_col_offset_bit6        ;
    int		                r_reg_ddrc_col_offset_bit7        ;
    int		                r_reg_ddrc_col_offset_bit8        ;
    int		                r_reg_ddrc_col_offset_bit9        ;
    int		                r_reg_ddrc_col_offset_bit10       ;
    int		                r_reg_ddrc_col_offset_bit11       ;

    int		                r_reg_ddrc_row_offset_bit0        ;
    int		                r_reg_ddrc_row_offset_bit1        ;
    int		                r_reg_ddrc_row_offset_bit2        ;
    int		                r_reg_ddrc_row_offset_bit3        ;
    int		                r_reg_ddrc_row_offset_bit4        ;
    int		                r_reg_ddrc_row_offset_bit5        ;
    int		                r_reg_ddrc_row_offset_bit6        ;
    int		                r_reg_ddrc_row_offset_bit7        ;
    int		                r_reg_ddrc_row_offset_bit8        ;
    int		                r_reg_ddrc_row_offset_bit9        ;
    int		                r_reg_ddrc_row_offset_bit10       ;
    int		                r_reg_ddrc_row_offset_bit11       ;
    int		                r_reg_ddrc_row_offset_bit12       ;
    int		                r_reg_ddrc_row_offset_bit13       ;
    int		                r_reg_ddrc_row_offset_bit14       ;
    int		                r_reg_ddrc_row_offset_bit15       ;
    int		                r_reg_ddrc_row_offset_bit16       ;
    int		                r_reg_ddrc_row_offset_bit17       ;

    int		                r_reg_ddrc_ba_offset_bit0         ;
    int		                r_reg_ddrc_ba_offset_bit1         ;
    int		                r_reg_ddrc_ba_offset_bit2         ;
    int		                r_reg_ddrc_ba_offset_bit3         ;

    int		                r_reg_ddrc_rank_offset_bit0       ;
    int		                r_reg_ddrc_rank_offset_bit1       ;


    
};   

struct train_result{
//////[rank_num][freq_sel][byte_num]
uint8_t dqs_calib_cycsel[4][4][4] ;
uint8_t dqs_calib_ophsel[4][4][4] ;
uint8_t dqs_calib_dllsel[4][4][4] ;

uint16_t rd_train_mid_for_dq0[4][4][4] ;
uint16_t rd_train_mid_for_dq1[4][4][4] ;
uint16_t rd_train_mid_for_dq2[4][4][4] ;
uint16_t rd_train_mid_for_dq3[4][4][4] ;
uint16_t rd_train_mid_for_dq4[4][4][4] ;
uint16_t rd_train_mid_for_dq5[4][4][4] ;
uint16_t rd_train_mid_for_dq6[4][4][4] ;
uint16_t rd_train_mid_for_dq7[4][4][4] ;
uint16_t rd_train_mid_for_dm [4][4][4] ;


uint16_t wr_train_mid_for_dq0[4][4][4] ;
uint16_t wr_train_mid_for_dq1[4][4][4] ;
uint16_t wr_train_mid_for_dq2[4][4][4] ;
uint16_t wr_train_mid_for_dq3[4][4][4] ;
uint16_t wr_train_mid_for_dq4[4][4][4] ;
uint16_t wr_train_mid_for_dq5[4][4][4] ;
uint16_t wr_train_mid_for_dq6[4][4][4] ;
uint16_t wr_train_mid_for_dq7[4][4][4] ;
uint16_t wr_train_mid_for_dm [4][4][4] ;


uint16_t rd_invdelay_dqs_value[4][4][4] ;
uint16_t wr_invdelay_dqs_value[4][4][4] ;

uint16_t	cha_perbit_skew_train_result_max[2][7];
uint16_t	chb_perbit_skew_train_result_max[2][7];
uint16_t	cha_perbit_skew_train_result_min[2][7];
uint16_t	chb_perbit_skew_train_result_min[2][7];

};


// RW REGISTER LIST

 #define	 reg_channel_en                  		  0x0		, 11		, 8		
 #define	 reg_burst_sel                   		  0x0		, 7		, 7		
 #define	 mem_select_t                    		  0x0		, 6		, 4		
 #define	 soft_reset1                     		  0x0		, 2		, 2		
 #define	 soft_reset0                     		  0x0		, 1		, 1		
 #define	 soft_reset                      		  0x0		, 0		, 0		
 #define	 reg_wl_loadmode                 		  0x4		, 31		, 16		
 #define	 reg_wlcs_sel                    		  0x4		, 7		, 6		
 #define	 reg_wl_bypass                   		  0x4		, 5		, 5		
 #define	 reg_wl_enable                   		  0x4		, 4		, 4		
 #define	 reg_calcs_sel                   		  0x4		, 3		, 2		
 #define	 reg_calib_bypass                		  0x4		, 1		, 1		
 #define	 reg_start_calib                 		  0x4		, 0		, 0		
 #define	 AL_FRE_OP0                      		  0x8		, 29		, 24		
 #define	 AL_FRE_OP1                      		  0x8		, 21		, 16		
 #define	 AL_FRE_OP2                      		  0x8		, 13		, 8		
 #define	 AL_FRE_OP3                      		  0x8		, 5		, 0		
 #define	 CL_FRE_OP0                      		  0xc		, 29		, 24		
 #define	 CL_FRE_OP1                      		  0xc		, 21		, 16		
 #define	 CL_FRE_OP2                      		  0xc		, 13		, 8		
 #define	 CL_FRE_OP3                      		  0xc		, 5		, 0		
 #define	 CWL_FRE_OP0                     		  0x10		, 28		, 24		
 #define	 CWL_FRE_OP1                     		  0x10		, 20		, 16		
 #define	 CWL_FRE_OP2                     		  0x10		, 12		, 8		
 #define	 CWL_FRE_OP3                     		  0x10		, 4		, 0		
 #define	 reg_fb1xclk_invdelaysel_dqcmd   		  0x14		, 28		, 24		
 #define	 reg_h4xclk_invdelaysel_dqcmd    		  0x14		, 20		, 16		
 #define	 reg_h4xclkdqs_invdelaysel_dqcmd 		  0x14		, 12		, 8		
 #define	 reg_h1xclk_invdelaysel_dqcmd    		  0x14		, 4		, 0		
 #define	 reg_cmd_ph90en_bp               		  0x18		, 31		, 0		
 #define	 reg_oscen_t                     		  0x1c		, 25		, 25		
 #define	 reg_x1clk_div_sel               		  0x1c		, 24		, 24		
 #define	 reg_vt_comp_bp                  		  0x1c		, 23		, 23		
 #define	 reg_cmdout_mux                  		  0x1c		, 22		, 22		
 #define	 ph90en_bp                       		  0x1c		, 21		, 21		
 #define	 ph90en_bp_dq                    		  0x1c		, 20		, 20		
 #define	 reg_rden_bypass                 		  0x1c		, 19		, 19		
 #define	 reg_rden_delay                  		  0x1c		, 18		, 16		
 #define	 reg_rdodt_bypass                		  0x1c		, 14		, 14		
 #define	 reg_rxodt_st_bypass             		  0x1c		, 13		, 13		
 #define	 reg_rxodt_stdelay               		  0x1c		, 11		, 8		
 #define	 reg_rxodt_length                		  0x1c		, 7		, 4		
 #define	 reg_rxodt_start_point           		  0x1c		, 3		, 0		
 #define	 reg_cat_rank_num                		  0x20		, 15		, 14		
 #define	 reg_cat_channel_num             		  0x20		, 13		, 12		
 #define	 reg_clk_div_cnt                 		  0x20		, 11		, 8		
 #define	 reg_cat_bp_rank_sel             		  0x20		, 7		, 6		
 #define	 reg_cat_bp_cmd_send             		  0x20		, 5		, 5		
 #define	 reg_cat_bp_mode                 		  0x20		, 4		, 4		
 #define	 reg_cat_bp_en                   		  0x20		, 3		, 3		
 #define	 reg_cat_bp_start                		  0x20		, 2		, 2		
 #define	 reg_cat_start                   		  0x20		, 1		, 1		
 #define	 reg_cat_enable                  		  0x20		, 0		, 0		
 #define	 reg_txcbt                       		  0x24		, 29		, 25		
 #define	 reg_tadr                        		  0x24		, 24		, 20		
 #define	 reg_tckelck                     		  0x24		, 19		, 15		
 #define	 reg_tdstrain                    		  0x24		, 14		, 10		
 #define	 reg_tmrw                        		  0x24		, 9		, 5		
 #define	 reg_tcacd                       		  0x24		, 4		, 0		
 #define	 reg_tvrefca_long                		  0x28		, 23		, 16		
 #define	 reg_tcaent                      		  0x28		, 15		, 8		
 #define	 reg_tfc                         		  0x28		, 7		, 0		
 #define	 reg_mr1                         		  0x2c		, 31		, 24		
 #define	 reg_mr2                         		  0x2c		, 23		, 16		
 #define	 reg_mr3                         		  0x2c		, 15		, 8		
 #define	 reg_mr11                        		  0x2c		, 7		, 0		
 #define	 reg_mr13                        		  0x30		, 23		, 16		
 #define	 reg_mr14                        		  0x30		, 15		, 8		
 #define	 reg_mr22                        		  0x30		, 7		, 0		
 #define	 reg_ca_vref_update              		  0x34		, 31		, 31		
 #define	 reg_cat_vref_scan_disable       		  0x34		, 30		, 30		
 #define	 reg_cat_vref_scan_max           		  0x34		, 29		, 24		
 #define	 reg_cat_vref_scan_min           		  0x34		, 21		, 16		
 #define	 reg_cha_cat_vref_bp_value       		  0x34		, 14		, 8		
 #define	 reg_chb_cat_vref_bp_value       		  0x34		, 6		, 0		
 #define	 reg_cs_perbit_skew_offest_fsp0  		  0x38		, 31		, 28		
 #define	 reg_cs_perbit_skew_offest_fsp1  		  0x38		, 27		, 24		
 #define	 reg_cs_perbit_skew_offest_fsp2  		  0x38		, 23		, 20		
 #define	 reg_cs_perbit_skew_offest_fsp3  		  0x38		, 19		, 16		
 #define	 reg_lpddr4_ca_odt               		  0x38		, 13		, 12		
 #define	 reg_lpddr4_ca_odt_sel           		  0x38		, 11		, 11		
 #define	 reg_cat_vref_scan_steps         		  0x38		, 10		, 8		
 #define	 reg_cs_pwc_disable              		  0x38		, 7		, 7		
 #define	 reg_cat_skip_fspy               		  0x38		, 6		, 6		
 #define	 reg_cat_fspy_rank               		  0x38		, 5		, 4		
 #define	 reg_cat_fc_pd_en                		  0x38		, 3		, 3		
 #define	 reg_cat_skip_cs_train           		  0x38		, 2		, 2		
 #define	 reg_cmd_perbit_skew_bp          		  0x38		, 1		, 1		
 #define	 reg_ca_perbit_skew_update       		  0x38		, 0		, 0		
 #define	 reg_cat_cke_mode                		  0x3c		, 25		, 25		
 #define	 reg_cat_ck_cke_odt_fix_perbit_skew		  0x3c		, 24		, 24		
 #define	 reg_cat_ca_scan_max             		  0x3c		, 23		, 16		
 #define	 reg_cat_ca_train_value          		  0x3c		, 13		, 8		
 #define	 reg_cat_cs_train_value          		  0x3c		, 5		, 0		
 #define	 reg_cha_cat_cs_check_value      		  0x40		, 29		, 24		
 #define	 reg_chb_cat_cs_check_value      		  0x40		, 21		, 16		
 #define	 reg_cha_cat_ca_check_value      		  0x40		, 13		, 8		
 #define	 reg_chb_cat_ca_check_value      		  0x40		, 5		, 0		
 #define	 reg_freq_choose_t               		  0x44		, 31		, 30		
 #define	 reg_lpddr4_rd_preamble          		  0x44		, 29		, 29		
 #define	 reg_wl_freq_update              		  0x44		, 28		, 28		
 #define	 reg_calib_freq_update           		  0x44		, 27		, 27		
 #define	 reg_cmd_abutobsmodeen           		  0x44		, 26		, 26		
 #define	 reg_sdram_vref_update           		  0x44		, 25		, 25		
 #define	 reg_calib_mode_sel              		  0x44		, 24		, 24		
 #define	 reg_pwrok_pi                    		  0x44		, 23		, 23		
 #define	 reg_lpddr4_cmd_gap_for_diff_rank		  0x44		, 22		, 20		
 #define	 reg_b0_cmdobsmuxsel             		  0x44		, 19		, 16		
 #define	 reg_b0_obsdataen                		  0x44		, 15		, 15		
 #define	 bist_calibst                    		  0x44		, 14		, 14		
 #define	 reg_fiford_delay                		  0x44		, 13		, 13		
 #define	 bist_ck_select                  		  0x44		, 12		, 12		
 #define	 reg_mch_odt                     		  0x44		, 11		, 11		
 #define	 mux_sync_sel                    		  0x44		, 10		, 10		
 #define	 reg_sync_en                     		  0x44		, 9		, 9		
 #define	 reg_rdptr_delay                 		  0x44		, 8		, 8		
 #define	 reg_scr_rcvmodsel               		  0x44		, 7		, 7		
 #define	 reg_scr_sckdimm0dis             		  0x44		, 6		, 6		
 #define	 reg_scr_sdhsclkb_pos1neg0sel    		  0x44		, 5		, 5		
 #define	 reg_scr_sdhsclk_pos1neg0sel     		  0x44		, 4		, 4		
 #define	 reg_scr_odttrien                		  0x44		, 3		, 3		
 #define	 reg_scr_csbtrien                		  0x44		, 2		, 2		
 #define	 reg_scr_cmdtrien                		  0x44		, 1		, 1		
 #define	 reg_scr_cketrirnk0              		  0x44		, 0		, 0		
 #define	 reg_ram_vref1_pd                		  0x48		, 12		, 12		
 #define	 bypassen                        		  0x48		, 11		, 8		
 #define	 reg_mpr_cnt                     		  0x48		, 7		, 0		
 #define	 reg_max_rdvalue                 		  0x4c		, 23		, 16		
 #define	 reg_calib_timeout               		  0x4c		, 15		, 0		
 #define	 reg_rrankdly_4x_dec             		  0x50		, 10		, 10		
 #define	 reg_rdrank_4xdly                		  0x50		, 9		, 8		
 #define	 reg_rdrank_delay_bp             		  0x50		, 7		, 7		
 #define	 reg_rdrank_1xdly                		  0x50		, 6		, 4		
 #define	 reg_wrrank_1xdly                		  0x50		, 2		, 0		
 #define	 reg_cmd0_wrap_sel               		  0x54		, 28		, 24		
 #define	 reg_cmd1_wrap_sel               		  0x54		, 20		, 16		
 #define	 reg_cmd2_wrap_sel               		  0x54		, 12		, 8		
 #define	 reg_cmd3_wrap_sel               		  0x54		, 4		, 0		
 #define	 reg_cmd4_wrap_sel               		  0x58		, 28		, 24		
 #define	 reg_cmd5_wrap_sel               		  0x58		, 20		, 16		
 #define	 reg_cmd6_wrap_sel               		  0x58		, 12		, 8		
 #define	 reg_cmd7_wrap_sel               		  0x58		, 4		, 0		
 #define	 reg_cmd8_wrap_sel               		  0x5c		, 28		, 24		
 #define	 reg_cmd9_wrap_sel               		  0x5c		, 20		, 16		
 #define	 reg_cmd10_wrap_sel              		  0x5c		, 12		, 8		
 #define	 reg_cmd11_wrap_sel              		  0x5c		, 4		, 0		
 #define	 reg_cmd12_wrap_sel              		  0x60		, 28		, 24		
 #define	 reg_cmd13_wrap_sel              		  0x60		, 20		, 16		
 #define	 reg_cmd14_wrap_sel              		  0x60		, 12		, 8		
 #define	 reg_cmd15_wrap_sel              		  0x60		, 4		, 0		
 #define	 reg_cmd16_wrap_sel              		  0x64		, 28		, 24		
 #define	 reg_cmd17_wrap_sel              		  0x64		, 20		, 16		
 #define	 reg_cmd18_wrap_sel              		  0x64		, 12		, 8		
 #define	 reg_cmd19_wrap_sel              		  0x64		, 4		, 0		
 #define	 reg_cmd20_wrap_sel              		  0x68		, 28		, 24		
 #define	 reg_cmd21_wrap_sel              		  0x68		, 20		, 16		
 #define	 reg_cmd22_wrap_sel              		  0x68		, 12		, 8		
 #define	 reg_cmd23_wrap_sel              		  0x68		, 4		, 0		
 #define	 reg_cmd24_wrap_sel              		  0x6c		, 28		, 24		
 #define	 reg_cmd25_wrap_sel              		  0x6c		, 20		, 16		
 #define	 reg_cmd26_wrap_sel              		  0x6c		, 12		, 8		
 #define	 reg_cmd27_wrap_sel              		  0x6c		, 4		, 0		
 #define	 reg_cmd28_wrap_sel              		  0x70		, 28		, 24		
 #define	 reg_cmd29_wrap_sel              		  0x70		, 20		, 16		
 #define	 reg_cmd30_wrap_sel              		  0x70		, 12		, 8		
 #define	 reg_byte0_wrap_sel              		  0x74		, 31		, 30		
 #define	 reg_byte1_wrap_sel              		  0x74		, 29		, 28		
 #define	 reg_byte2_wrap_sel              		  0x74		, 27		, 26		
 #define	 reg_byte3_wrap_sel              		  0x74		, 25		, 24		
 #define	 reg_cke_ck_cmd_pad_t            		  0x78		, 31		, 0		
 #define	 reg_pllfbdiv_dqcmd              		  0x7c		, 24		, 16		
 #define	 reg_pllprediv_dqcmd             		  0x7c		, 8		, 4		
 #define	 reg_pllpostdiven_dqcmd          		  0x7c		, 3		, 3		
 #define	 reg_pllpostdiv_dqcmd            		  0x7c		, 2		, 0		
 #define	 reg_plltestsel_dqcmd            		  0x80		, 19		, 18		
 #define	 reg_pllgvco_bias_dqcmd          		  0x80		, 17		, 16		
 #define	 reg_pllcpi_bias_dqcmd           		  0x80		, 14		, 12		
 #define	 reg_pllcpp_bias_dqcmd           		  0x80		, 10		, 8		
 #define	 reg_plltestouten_dqcmd          		  0x80		, 7		, 7		
 #define	 reg_lockenb_dqcmd               		  0x80		, 6		, 6		
 #define	 reg_pllrstbsel_dqcmd            		  0x80		, 5		, 5		
 #define	 reg_pllref_clk_byp_dqcmd        		  0x80		, 4		, 4		
 #define	 reg_ssc_rstn                    		  0x80		, 3		, 3		
 #define	 reg_pllincz_dqcmd               		  0x80		, 2		, 2		
 #define	 reg_pllclkouten_dqcmd_t         		  0x80		, 1		, 1		
 #define	 reg_pllpd_dqcmd_t               		  0x80		, 0		, 0		
 #define	 reg_dfi_clk_gate_bp             		  0x84		, 28		, 28		
 #define	 reg_hclk_train_sel              		  0x84		, 27		, 27		
 #define	 reg_hclk_bist_sel               		  0x84		, 26		, 26		
 #define	 reg_hclk_zqcalib_sel            		  0x84		, 25		, 25		
 #define	 reg_hclk_byte0_sel              		  0x84		, 24		, 24		
 #define	 reg_hclk_byte1_sel              		  0x84		, 23		, 23		
 #define	 reg_hclk_byte2_sel              		  0x84		, 22		, 22		
 #define	 reg_hclk_byte3_sel              		  0x84		, 21		, 21		
 #define	 reg_hclk_byte_sel               		  0x84		, 20		, 20		
 #define	 reg_hclk_ca_sel                 		  0x84		, 19		, 19		
 #define	 reg_train_reg_update_en         		  0x84		, 18		, 18		
 #define	 reg_dqclken_t                   		  0x84		, 17		, 17		
 #define	 reg_outclken                    		  0x84		, 16		, 16		
 #define	 reg_lp_bypass                   		  0x84		, 15		, 15		
 #define	 reg_deep_lp_en                  		  0x84		, 14		, 14		
 #define	 reg_lp_wakeup_sel               		  0x84		, 13		, 13		
 #define	 reg_lp_vref_ctrl_en             		  0x84		, 12		, 12		
 #define	 reg_lp_wakeup_threhold          		  0x84		, 11		, 8		
 #define	 reg_lp_io_dis_ctrl              		  0x84		, 7		, 6		
 #define	 reg_lp_dq_clk_ctrl_en           		  0x84		, 5		, 5		
 #define	 reg_lp_dig_rst_ctrl_en          		  0x84		, 4		, 4		
 #define	 reg_lp_spll_clktree_ctrl_en     		  0x84		, 3		, 3		
 #define	 reg_lp_dig_clk_ctrl_en          		  0x84		, 2		, 2		
 #define	 reg_lp_io_ctrl_en               		  0x84		, 1		, 1		
 #define	 reg_lp_pllpd_ctrl_en            		  0x84		, 0		, 0		
 #define	 reg_lp_stvalue                  		  0x88		, 23		, 20		
 #define	 reg_lp_ackvalue                 		  0x88		, 19		, 16		
 #define	 reg_wait_cnt                    		  0x88		, 15		, 0		
 #define	 reg_zq_chg_interval             		  0x8c		, 28		, 20		
 #define	 reg_pu_interval                 		  0x8c		, 18		, 10		
 #define	 reg_odtpu_zqcalib_sel           		  0x8c		, 9		, 8		
 #define	 reg_drvpu_zqcalib_sel           		  0x8c		, 7		, 6		
 #define	 reg_sel_zqcali                  		  0x8c		, 5		, 4		
 #define	 reg_pd_zqcali                   		  0x8c		, 3		, 3		
 #define	 reg_zqcali_clear                		  0x8c		, 2		, 2		
 #define	 reg_zqcali_bypass               		  0x8c		, 1		, 1		
 #define	 reg_zqcali_en                   		  0x8c		, 0		, 0		
 #define	 reg_drvlegn_zqcali              		  0x90		, 28		, 24		
 #define	 reg_drvlegpb_zqcali             		  0x90		, 20		, 16		
 #define	 reg_odtlegn_zqcali              		  0x90		, 12		, 8		
 #define	 reg_odtlegpb_zqcali             		  0x90		, 4		, 0		
 #define	 reg_pd_interval                 		  0x94		, 22		, 14		
 #define	 reg_rd_train_perdef_en          		  0x94		, 12		, 12		
 #define	 reg_train_vref_en               		  0x94		, 11		, 11		
 #define	 reg_ddr4_dbi                    		  0x94		, 10		, 10		
 #define	 reg_rdtrain_cs_sel              		  0x94		, 9		, 8		
 #define	 reg_rx_vref_value_update        		  0x94		, 7		, 7		
 #define	 reg_rd_train_dqs_range_bypass   		  0x94		, 6		, 6		
 #define	 reg_bypass_rd_train_cmd_start_en		  0x94		, 5		, 5		
 #define	 reg_bypass_rd_train_en          		  0x94		, 4		, 4		
 #define	 reg_rd_train_check_value_en     		  0x94		, 3		, 3		
 #define	 reg_rd_train_freq_update        		  0x94		, 2		, 2		
 #define	 reg_dqs_rd_train_en             		  0x94		, 1		, 1		
 #define	 reg_dq_rd_train_en              		  0x94		, 0		, 0		
 #define	 reg_lpddr4_mr15_value           		  0x98		, 31		, 24		
 #define	 reg_lpddr4_mr20_value           		  0x98		, 23		, 16		
 #define	 reg_lpddr4_mr32_value           		  0x98		, 15		, 8		
 #define	 reg_lpddr4_mr40_value           		  0x98		, 7		, 0		
 #define	 reg_ddr4_mr4_value              		  0x9c		, 31		, 16		
 #define	 reg_ddr4_mr3                    		  0x9c		, 7		, 0		
 #define	 reg_wrtrain_lpddr4_vref_range   		  0xa0		, 22		, 22		
 #define	 reg_pbit_deskew_offset_for_lpddr4		  0xa0		, 21		, 16		
 #define	 reg_dqs_wr_train_en             		  0xa0		, 9		, 9		
 #define	 reg_wrtrain_check_data_value_random_gen		  0xa0		, 8		, 8		
 #define	 reg_wrtrain_cs_sel              		  0xa0		, 7		, 6		
 #define	 reg_wr_train_rst                		  0xa0		, 5		, 5		
 #define	 reg_wr_train_dqs_default_bypass 		  0xa0		, 4		, 4		
 #define	 reg_wr_train_dqs_range_bypass   		  0xa0		, 3		, 3		
 #define	 reg_wr_train_freq_update        		  0xa0		, 2		, 2		
 #define	 reg_dq_wr_train_en              		  0xa0		, 1		, 1		
 #define	 reg_dq_wr_train_auto            		  0xa0		, 0		, 0		
 #define	 reg_wr_train_ba_addr            		  0xa4		, 30		, 28		
 #define	 reg_wr_train_col_addr           		  0xa4		, 25		, 16		
 #define	 reg_wr_train_row_addr           		  0xa4		, 15		, 0		
 #define	 reg_phy_trefi                   		  0xa8		, 31		, 18		
 #define	 reg_phy_trfc                    		  0xa8		, 17		, 8		
 #define	 reg_max_refi_cnt                		  0xa8		, 7		, 4		
 #define	 reg_phy_refresh_en              		  0xa8		, 0		, 0		
 #define	 reg_ddrphy_trp                  		  0xac		, 19		, 12		
 #define	 reg_data_path_clk_gate_dly      		  0xac		, 11		, 6		
 #define	 reg_data_path_clk_gate_dly_bp   		  0xac		, 5		, 5		
 #define	 reg_freq_choose_bypass          		  0xac		, 4		, 4		
 #define	 reg_all_freq_train_finish       		  0xac		, 3		, 3		
 #define	 reg_pll_lock_bypass             		  0xac		, 2		, 2		
 #define	 reg_pllpd_bypass                		  0xac		, 1		, 1		
 #define	 reg_lpddr4_write_postamble_sel  		  0xac		, 0		, 0		
 #define	 reg_wl_dqs_lock_point           		  0xb0		, 27		, 22		
 #define	 reg_wl_dqs_start_point          		  0xb0		, 21		, 16		
 #define	 reg_rd_train_dqs_scan_max       		  0xb0		, 13		, 8		
 #define	 reg_rd_train_dq_scan_max        		  0xb0		, 5		, 0		
 #define	 reg_cmd_drv_zqcalib_en          		  0xf0		, 16		, 16		
 #define	 reg_cmd_fbsel_reg               		  0xf0		, 15		, 15		
 #define	 reg_cmd_fben_reg                		  0xf0		, 14		, 14		
 #define	 reg_cmd_abutweakpub_reg         		  0xf0		, 13		, 13		
 #define	 reg_cmd_abutslewpu_reg          		  0xf0		, 12		, 8		
 #define	 reg_cmd_abutweakpd_reg          		  0xf0		, 5		, 5		
 #define	 reg_cmd_abutslewpd_reg          		  0xf0		, 4		, 0		
 #define	 reg_cmd_abutnrcomp4_reg         		  0xf4		, 28		, 28		
 #define	 reg_cmd_abutnrcomp3_reg         		  0xf4		, 27		, 27		
 #define	 reg_cmd_abutnrcomp2_reg         		  0xf4		, 26		, 26		
 #define	 reg_cmd_abutnrcomp1_reg         		  0xf4		, 25		, 25		
 #define	 reg_cmd_abutnrcomp0_reg         		  0xf4		, 24		, 24		
 #define	 reg_cmd_abutprcomp4_reg         		  0xf4		, 20		, 20		
 #define	 reg_cmd_abutprcomp3_reg         		  0xf4		, 19		, 19		
 #define	 reg_cmd_abutprcomp2_reg         		  0xf4		, 18		, 18		
 #define	 reg_cmd_abutprcomp1_reg         		  0xf4		, 17		, 17		
 #define	 reg_cmd_abutprcomp0_reg         		  0xf4		, 16		, 16		
 #define	 reg_cmd_abutnrcomp4_ck0_reg     		  0xf4		, 12		, 12		
 #define	 reg_cmd_abutnrcomp3_ck0_reg     		  0xf4		, 11		, 11		
 #define	 reg_cmd_abutnrcomp2_ck0_reg     		  0xf4		, 10		, 10		
 #define	 reg_cmd_abutnrcomp1_ck0_reg     		  0xf4		, 9		, 9		
 #define	 reg_cmd_abutnrcomp0_ck0_reg     		  0xf4		, 8		, 8		
 #define	 reg_cmd_abutprcomp4_ck0_reg     		  0xf4		, 4		, 4		
 #define	 reg_cmd_abutprcomp3_ck0_reg     		  0xf4		, 3		, 3		
 #define	 reg_cmd_abutprcomp2_ck0_reg     		  0xf4		, 2		, 2		
 #define	 reg_cmd_abutprcomp1_ck0_reg     		  0xf4		, 1		, 1		
 #define	 reg_cmd_abutprcomp0_ck0_reg     		  0xf4		, 0		, 0		
 #define	 reg_ram_vref1_margsel_reg       		  0xf8		, 23		, 16		
 #define	 reg_cmd_abutnrcomp4_special_reg 		  0xf8		, 12		, 12		
 #define	 reg_cmd_abutnrcomp3_special_reg 		  0xf8		, 11		, 11		
 #define	 reg_cmd_abutnrcomp2_special_reg 		  0xf8		, 10		, 10		
 #define	 reg_cmd_abutnrcomp1_special_reg 		  0xf8		, 9		, 9		
 #define	 reg_cmd_abutnrcomp0_special_reg 		  0xf8		, 8		, 8		
 #define	 reg_cmd_abutprcomp4_special_reg 		  0xf8		, 4		, 4		
 #define	 reg_cmd_abutprcomp3_special_reg 		  0xf8		, 3		, 3		
 #define	 reg_cmd_abutprcomp2_special_reg 		  0xf8		, 2		, 2		
 #define	 reg_cmd_abutprcomp1_special_reg 		  0xf8		, 1		, 1		
 #define	 reg_cmd_abutprcomp0_special_reg 		  0xf8		, 0		, 0		
 #define	 reg_a0_invdelaysel_bp           		  0x104		, 29		, 24		
 #define	 reg_a1_invdelaysel_bp           		  0x104		, 21		, 16		
 #define	 reg_a2_invdelaysel_bp           		  0x104		, 13		, 8		
 #define	 reg_a3_invdelaysel_bp           		  0x104		, 5		, 0		
 #define	 reg_a4_invdelaysel_bp           		  0x108		, 29		, 24		
 #define	 reg_a5_invdelaysel_bp           		  0x108		, 21		, 16		
 #define	 reg_a6_invdelaysel_bp           		  0x108		, 13		, 8		
 #define	 reg_a7_invdelaysel_bp           		  0x108		, 5		, 0		
 #define	 reg_a8_invdelaysel_bp           		  0x10c		, 29		, 24		
 #define	 reg_a9_invdelaysel_bp           		  0x10c		, 21		, 16		
 #define	 reg_a10_invdelaysel_bp          		  0x10c		, 13		, 8		
 #define	 reg_a11_invdelaysel_bp          		  0x10c		, 5		, 0		
 #define	 reg_a12_invdelaysel_bp          		  0x110		, 29		, 24		
 #define	 reg_a13_invdelaysel_bp          		  0x110		, 21		, 16		
 #define	 reg_a14_invdelaysel_bp          		  0x110		, 13		, 8		
 #define	 reg_a15_invdelaysel_bp          		  0x110		, 5		, 0		
 #define	 reg_a16_invdelaysel_bp          		  0x114		, 29		, 24		
 #define	 reg_a17_invdelaysel_bp          		  0x114		, 21		, 16		
 #define	 reg_ba0_invdelaysel_bp          		  0x114		, 13		, 8		
 #define	 reg_ba1_invdelaysel_bp          		  0x114		, 5		, 0		
 #define	 reg_bg0_invdelaysel_bp          		  0x118		, 29		, 24		
 #define	 reg_bg1_invdelaysel_bp          		  0x118		, 21		, 16		
 #define	 reg_cke0_invdelaysel_bp         		  0x118		, 13		, 8		
 #define	 reg_cke1_invdelaysel_bp         		  0x118		, 5		, 0		
 #define	 reg_ckb_invdelaysel_bp          		  0x11c		, 29		, 24		
 #define	 reg_ck_invdelaysel_bp           		  0x11c		, 21		, 16		
 #define	 reg_odt0_invdelaysel_bp         		  0x11c		, 13		, 8		
 #define	 reg_odt1_invdelaysel_bp         		  0x11c		, 5		, 0		
 #define	 reg_csb0_invdelaysel_bp         		  0x120		, 29		, 24		
 #define	 reg_csb1_invdelaysel_bp         		  0x120		, 21		, 16		
 #define	 reg_resetn_invdelaysel_bp       		  0x120		, 13		, 8		
 #define	 reg_actn_invdelaysel_bp         		  0x120		, 5		, 0		
 #define	 dq0_train_check_data_value0     		  0x150		, 31		, 24		
 #define	 dq0_train_check_data_value1     		  0x150		, 23		, 16		
 #define	 dq0_train_check_data_value2     		  0x150		, 15		, 8		
 #define	 dq0_train_check_data_value3     		  0x150		, 7		, 0		
 #define	 dq0_train_check_data_value4     		  0x154		, 31		, 24		
 #define	 dq0_train_check_data_value5     		  0x154		, 23		, 16		
 #define	 dq0_train_check_data_value6     		  0x154		, 15		, 8		
 #define	 dq0_train_check_data_value7     		  0x154		, 7		, 0		
 #define	 dq0_train_check_data_value8     		  0x158		, 15		, 8		
 #define	 dq0_train_check_data_value9     		  0x158		, 7		, 0		
 #define	 dq1_train_check_data_value0     		  0x15c		, 31		, 24		
 #define	 dq1_train_check_data_value1     		  0x15c		, 23		, 16		
 #define	 dq1_train_check_data_value2     		  0x15c		, 15		, 8		
 #define	 dq1_train_check_data_value3     		  0x15c		, 7		, 0		
 #define	 dq1_train_check_data_value4     		  0x160		, 31		, 24		
 #define	 dq1_train_check_data_value5     		  0x160		, 23		, 16		
 #define	 dq1_train_check_data_value6     		  0x160		, 15		, 8		
 #define	 dq1_train_check_data_value7     		  0x160		, 7		, 0		
 #define	 dq1_train_check_data_value8     		  0x164		, 15		, 8		
 #define	 dq1_train_check_data_value9     		  0x164		, 7		, 0		
 #define	 dq2_train_check_data_value0     		  0x168		, 31		, 24		
 #define	 dq2_train_check_data_value1     		  0x168		, 23		, 16		
 #define	 dq2_train_check_data_value2     		  0x168		, 15		, 8		
 #define	 dq2_train_check_data_value3     		  0x168		, 7		, 0		
 #define	 dq2_train_check_data_value4     		  0x16c		, 31		, 24		
 #define	 dq2_train_check_data_value5     		  0x16c		, 23		, 16		
 #define	 dq2_train_check_data_value6     		  0x16c		, 15		, 8		
 #define	 dq2_train_check_data_value7     		  0x16c		, 7		, 0		
 #define	 dq2_train_check_data_value8     		  0x170		, 15		, 8		
 #define	 dq2_train_check_data_value9     		  0x170		, 7		, 0		
 #define	 dq3_train_check_data_value0     		  0x174		, 31		, 24		
 #define	 dq3_train_check_data_value1     		  0x174		, 23		, 16		
 #define	 dq3_train_check_data_value2     		  0x174		, 15		, 8		
 #define	 dq3_train_check_data_value3     		  0x174		, 7		, 0		
 #define	 dq3_train_check_data_value4     		  0x178		, 31		, 24		
 #define	 dq3_train_check_data_value5     		  0x178		, 23		, 16		
 #define	 dq3_train_check_data_value6     		  0x178		, 15		, 8		
 #define	 dq3_train_check_data_value7     		  0x178		, 7		, 0		
 #define	 dq3_train_check_data_value8     		  0x17c		, 15		, 8		
 #define	 dq3_train_check_data_value9     		  0x17c		, 7		, 0		
 #define	 dq4_train_check_data_value0     		  0x180		, 31		, 24		
 #define	 dq4_train_check_data_value1     		  0x180		, 23		, 16		
 #define	 dq4_train_check_data_value2     		  0x180		, 15		, 8		
 #define	 dq4_train_check_data_value3     		  0x180		, 7		, 0		
 #define	 dq4_train_check_data_value4     		  0x184		, 31		, 24		
 #define	 dq4_train_check_data_value5     		  0x184		, 23		, 16		
 #define	 dq4_train_check_data_value6     		  0x184		, 15		, 8		
 #define	 dq4_train_check_data_value7     		  0x184		, 7		, 0		
 #define	 dq4_train_check_data_value8     		  0x188		, 15		, 8		
 #define	 dq4_train_check_data_value9     		  0x188		, 7		, 0		
 #define	 dq5_train_check_data_value0     		  0x18c		, 31		, 24		
 #define	 dq5_train_check_data_value1     		  0x18c		, 23		, 16		
 #define	 dq5_train_check_data_value2     		  0x18c		, 15		, 8		
 #define	 dq5_train_check_data_value3     		  0x18c		, 7		, 0		
 #define	 dq5_train_check_data_value4     		  0x190		, 31		, 24		
 #define	 dq5_train_check_data_value5     		  0x190		, 23		, 16		
 #define	 dq5_train_check_data_value6     		  0x190		, 15		, 8		
 #define	 dq5_train_check_data_value7     		  0x190		, 7		, 0		
 #define	 dq5_train_check_data_value8     		  0x194		, 15		, 8		
 #define	 dq5_train_check_data_value9     		  0x194		, 7		, 0		
 #define	 dq6_train_check_data_value0     		  0x198		, 31		, 24		
 #define	 dq6_train_check_data_value1     		  0x198		, 23		, 16		
 #define	 dq6_train_check_data_value2     		  0x198		, 15		, 8		
 #define	 dq6_train_check_data_value3     		  0x198		, 7		, 0		
 #define	 dq6_train_check_data_value4     		  0x19c		, 31		, 24		
 #define	 dq6_train_check_data_value5     		  0x19c		, 23		, 16		
 #define	 dq6_train_check_data_value6     		  0x19c		, 15		, 8		
 #define	 dq6_train_check_data_value7     		  0x19c		, 7		, 0		
 #define	 dq6_train_check_data_value8     		  0x1a0		, 15		, 8		
 #define	 dq6_train_check_data_value9     		  0x1a0		, 7		, 0		
 #define	 dq7_train_check_data_value0     		  0x1a4		, 31		, 24		
 #define	 dq7_train_check_data_value1     		  0x1a4		, 23		, 16		
 #define	 dq7_train_check_data_value2     		  0x1a4		, 15		, 8		
 #define	 dq7_train_check_data_value3     		  0x1a4		, 7		, 0		
 #define	 dq7_train_check_data_value4     		  0x1a8		, 31		, 24		
 #define	 dq7_train_check_data_value5     		  0x1a8		, 23		, 16		
 #define	 dq7_train_check_data_value6     		  0x1a8		, 15		, 8		
 #define	 dq7_train_check_data_value7     		  0x1a8		, 7		, 0		
 #define	 reg_wrtrain_odt_advance         		  0x1ac		, 19		, 19		
 #define	 reg_wrtrain_odt_keep            		  0x1ac		, 18		, 16		
 #define	 dq7_train_check_data_value8     		  0x1ac		, 15		, 8		
 #define	 dq7_train_check_data_value9     		  0x1ac		, 7		, 0		
 #define	 reg_wrtrain_vref_wait_vref_cnt_50ns		  0x1b0		, 31		, 24		
 #define	 reg_train_vref_step_min         		  0x1b0		, 23		, 21		
 #define	 reg_train_vref_step_max         		  0x1b0		, 20		, 16		
 #define	 reg_cmd_invdelaysel_sel         		  0x1b0		, 15		, 10		
 #define	 reg_rdtrain_wait_vref_valid_cnt 		  0x1b0		, 9		, 0		


// RO REGISTER LIST
 #define	 train_all_step_done             		  0x1f0		, 7		, 7		
 #define	 train_step1_delay_done          		  0x1f0		, 6		, 6		
 #define	 train_step2_vref_done           		  0x1f0		, 5		, 5		
 #define	 train_step3_delay_done          		  0x1f0		, 4		, 4		
 #define	 train_step1_error               		  0x1f0		, 3		, 3		
 #define	 train_step2_error               		  0x1f0		, 2		, 2		
 #define	 train_step3_error               		  0x1f0		, 1		, 1		
 #define	 train_true_done                 		  0x1f0		, 0		, 0		
 #define	 user_load_mode_busy             		  0x1f4		, 4		, 4		
 #define	 pwrok_reg_po                    		  0x1f4		, 3		, 3		
 #define	 pwrokcore                       		  0x1f4		, 2		, 2		
 #define	 lock_mpll                       		  0x1f4		, 1		, 1		
 #define	 lock_pll_dqcmd                  		  0x1f4		, 0		, 0		
 #define	 drvlegn_zqcali_2reg             		  0x1f8		, 28		, 24		
 #define	 drvlegpb_zqcali_2reg            		  0x1f8		, 20		, 16		
 #define	 odtlegn_zqcali_2reg             		  0x1f8		, 12		, 8		
 #define	 odtlegpb_zqcali_2reg            		  0x1f8		, 4		, 0		
 #define	 reg_x1clk_ndiv_cnt              		  0x1fc		, 18		, 8		
 #define	 reg_zqcali_done                 		  0x1fc		, 4		, 4		
 #define	 reg_drvpd_overflow              		  0x1fc		, 3		, 3		
 #define	 reg_drvpu_overflow              		  0x1fc		, 2		, 2		
 #define	 reg_odtpd_overflow              		  0x1fc		, 1		, 1		
 #define	 reg_odtpu_overflow              		  0x1fc		, 0		, 0		
 #define	 cmd_error_flag                  		  0x200		, 3		, 3		
 #define	 dm_error_flag                   		  0x200		, 2		, 2		
 #define	 dq_error_flag                   		  0x200		, 1		, 1		
 #define	 bist_complete                   		  0x200		, 0		, 0		
 #define	 bist_error_dq                   		  0x204		, 31		, 0		
 #define	 bist_error_dm                   		  0x208		, 31		, 28		
 #define	 bist_error_cmd                  		  0x208		, 27		, 0		
 #define	 wl_done_byte                    		  0x20c		, 11		, 8		
 #define	 calib_end                       		  0x20c		, 5		, 5		
 #define	 calib_error                     		  0x20c		, 4		, 4		
 #define	 calib_done_byte                 		  0x20c		, 3		, 0		
 #define	 cha_rank_cat_bp_cmd_send_rdy    		  0x210		, 19		, 18		
 #define	 chb_rank_cat_bp_cmd_send_rdy    		  0x210		, 17		, 16		
 #define	 cha_rank_cat_bp_done            		  0x210		, 15		, 14		
 #define	 chb_rank_cat_bp_done            		  0x210		, 13		, 12		
 #define	 ca_check_value                  		  0x210		, 11		, 0		
 #define	 cha_cat_auto_cs_train_err       		  0x214		, 23		, 16		
 #define	 chb_cat_auto_cs_train_err       		  0x214		, 15		, 8		
 #define	 cha_cat_done                    		  0x214		, 3		, 3		
 #define	 chb_cat_done                    		  0x214		, 2		, 2		
 #define	 cha_cat_bp_cmd_send_done        		  0x214		, 1		, 1		
 #define	 chb_cat_bp_cmd_send_done        		  0x214		, 0		, 0		
 #define	 reg_cmd_invdelaysel             		  0x230		, 21		, 16		
 #define	 reg_wrtrain_vref_max_value      		  0x230		, 13		, 8		
 #define	 reg_wrtrain_vref_min_value      		  0x230		, 5		, 0		
 #define	 cha_rank0_ca0_min_perbit_skew_pass		  0x234		, 29		, 24		
 #define	 cha_rank0_ca1_min_perbit_skew_pass		  0x234		, 21		, 16		
 #define	 cha_rank0_ca2_min_perbit_skew_pass		  0x234		, 13		, 8		
 #define	 cha_rank0_ca3_min_perbit_skew_pass		  0x234		, 5		, 0		
 #define	 cha_rank0_ca4_min_perbit_skew_pass		  0x238		, 29		, 24		
 #define	 cha_rank0_ca5_min_perbit_skew_pass		  0x238		, 21		, 16		
 #define	 cha_rank1_ca0_min_perbit_skew_pass		  0x238		, 13		, 8		
 #define	 cha_rank1_ca1_min_perbit_skew_pass		  0x238		, 5		, 0		
 #define	 cha_rank1_ca2_min_perbit_skew_pass		  0x23c		, 29		, 24		
 #define	 cha_rank1_ca3_min_perbit_skew_pass		  0x23c		, 21		, 16		
 #define	 cha_rank1_ca4_min_perbit_skew_pass		  0x23c		, 13		, 8		
 #define	 cha_rank1_ca5_min_perbit_skew_pass		  0x23c		, 5		, 0		
 #define	 cha_rank0_min_cs_perbit_skew_pass		  0x240		, 29		, 24		
 #define	 cha_rank1_min_cs_perbit_skew_pass		  0x240		, 21		, 16		
 #define	 cha_rank0_max_cs_perbit_skew_pass		  0x240		, 13		, 8		
 #define	 cha_rank1_max_cs_perbit_skew_pass		  0x240		, 5		, 0		
 #define	 cha_rank0_ca0_max_perbit_skew_pass		  0x244		, 29		, 24		
 #define	 cha_rank0_ca1_max_perbit_skew_pass		  0x244		, 21		, 16		
 #define	 cha_rank0_ca2_max_perbit_skew_pass		  0x244		, 13		, 8		
 #define	 cha_rank0_ca3_max_perbit_skew_pass		  0x244		, 5		, 0		
 #define	 cha_rank0_ca4_max_perbit_skew_pass		  0x248		, 29		, 24		
 #define	 cha_rank0_ca5_max_perbit_skew_pass		  0x248		, 21		, 16		
 #define	 cha_rank1_ca0_max_perbit_skew_pass		  0x248		, 13		, 8		
 #define	 cha_rank1_ca1_max_perbit_skew_pass		  0x248		, 5		, 0		
 #define	 cha_rank1_ca2_max_perbit_skew_pass		  0x24c		, 29		, 24		
 #define	 cha_rank1_ca3_max_perbit_skew_pass		  0x24c		, 21		, 16		
 #define	 cha_rank1_ca4_max_perbit_skew_pass		  0x24c		, 13		, 8		
 #define	 cha_rank1_ca5_max_perbit_skew_pass		  0x24c		, 5		, 0		
 #define	 chb_rank0_ca0_min_perbit_skew_pass		  0x250		, 29		, 24		
 #define	 chb_rank0_ca1_min_perbit_skew_pass		  0x250		, 21		, 16		
 #define	 chb_rank0_ca2_min_perbit_skew_pass		  0x250		, 13		, 8		
 #define	 chb_rank0_ca3_min_perbit_skew_pass		  0x250		, 5		, 0		
 #define	 chb_rank0_ca4_min_perbit_skew_pass		  0x254		, 29		, 24		
 #define	 chb_rank0_ca5_min_perbit_skew_pass		  0x254		, 21		, 16		
 #define	 chb_rank1_ca0_min_perbit_skew_pass		  0x254		, 13		, 8		
 #define	 chb_rank1_ca1_min_perbit_skew_pass		  0x254		, 5		, 0		
 #define	 chb_rank1_ca2_min_perbit_skew_pass		  0x258		, 29		, 24		
 #define	 chb_rank1_ca3_min_perbit_skew_pass		  0x258		, 21		, 16		
 #define	 chb_rank1_ca4_min_perbit_skew_pass		  0x258		, 13		, 8		
 #define	 chb_rank1_ca5_min_perbit_skew_pass		  0x258		, 5		, 0		
 #define	 chb_rank0_min_cs_perbit_skew_pass		  0x25c		, 29		, 24		
 #define	 chb_rank1_min_cs_perbit_skew_pass		  0x25c		, 21		, 16		
 #define	 chb_rank0_max_cs_perbit_skew_pass		  0x25c		, 13		, 8		
 #define	 chb_rank1_max_cs_perbit_skew_pass		  0x25c		, 5		, 0		
 #define	 chb_rank0_ca0_max_perbit_skew_pass		  0x260		, 29		, 24		
 #define	 chb_rank0_ca1_max_perbit_skew_pass		  0x260		, 21		, 16		
 #define	 chb_rank0_ca2_max_perbit_skew_pass		  0x260		, 13		, 8		
 #define	 chb_rank0_ca3_max_perbit_skew_pass		  0x260		, 5		, 0		
 #define	 chb_rank0_ca4_max_perbit_skew_pass		  0x264		, 29		, 24		
 #define	 chb_rank0_ca5_max_perbit_skew_pass		  0x264		, 21		, 16		
 #define	 chb_rank1_ca0_max_perbit_skew_pass		  0x264		, 13		, 8		
 #define	 chb_rank1_ca1_max_perbit_skew_pass		  0x264		, 5		, 0		
 #define	 chb_rank1_ca2_max_perbit_skew_pass		  0x268		, 29		, 24		
 #define	 chb_rank1_ca3_max_perbit_skew_pass		  0x268		, 21		, 16		
 #define	 chb_rank1_ca4_max_perbit_skew_pass		  0x268		, 13		, 8		
 #define	 chb_rank1_ca5_max_perbit_skew_pass		  0x268		, 5		, 0		
 #define	 cha_rank0_min_cs_vref_pass      		  0x26c		, 29		, 24		
 #define	 cha_rank0_max_cs_vref_pass      		  0x26c		, 21		, 16		
 #define	 cha_rank1_min_cs_vref_pass      		  0x26c		, 13		, 8		
 #define	 cha_rank1_max_cs_vref_pass      		  0x26c		, 5		, 0		
 #define	 chb_rank0_min_cs_vref_pass      		  0x270		, 29		, 24		
 #define	 chb_rank0_max_cs_vref_pass      		  0x270		, 21		, 16		
 #define	 chb_rank1_min_cs_vref_pass      		  0x270		, 13		, 8		
 #define	 chb_rank1_max_cs_vref_pass      		  0x270		, 5		, 0		
 #define	 reg_rd_train_readback_data_valid_byte		  0x274		, 19		, 16		
 #define	 reg_train_done_for_rd_to_reg    		  0x274		, 15		, 12		
 #define	 reg_train_error_for_rd_byte     		  0x274		, 11		, 8		
 #define	 reg_wr_train_done_byte          		  0x274		, 7		, 4		
 #define	 reg_wr_train_error_byte         		  0x274		, 3		, 0		



// RW REGISTER LIST

 #define	 reg_b_l_vref1_margsel_reg       		  0x600		, 31		, 24		
 #define	 reg_b_l_dq_odt_zqcali_en        		  0x600		, 22		, 22		
 #define	 reg_b_l_dq_drv_zqcali_en        		  0x600		, 21		, 21		
 #define	 reg_b_l_abutweakpddq_reg        		  0x600		, 20		, 20		
 #define	 reg_b_l_abutweakpubdq_reg       		  0x600		, 19		, 19		
 #define	 reg_b_l_abutdiffampseen_reg     		  0x600		, 18		, 18		
 #define	 reg_b_l_dqfben_reg              		  0x600		, 17		, 17		
 #define	 reg_b_l_dqfbsel_reg             		  0x600		, 16		, 16		
 #define	 reg_b_l_vref1_pd_reg            		  0x600		, 15		, 15		
 #define	 reg_b_l_weakpd_reg              		  0x600		, 14		, 14		
 #define	 reg_b_l_weakpub_reg             		  0x600		, 13		, 13		
 #define	 reg_b_l_abutslewpu_reg          		  0x600		, 12		, 8		
 #define	 reg_b_l_enb_lp4mode_reg         		  0x600		, 7		, 7		
 #define	 reg_b_l_dqsweakpd_reg           		  0x600		, 6		, 6		
 #define	 reg_b_l_dqsbweakpub_reg         		  0x600		, 5		, 5		
 #define	 reg_b_l_abutslewpd_reg          		  0x600		, 4		, 0		
 #define	 reg_b_l_abutnrcompdq4_reg       		  0x604		, 28		, 28		
 #define	 reg_b_l_abutnrcompdq3_reg       		  0x604		, 27		, 27		
 #define	 reg_b_l_abutnrcompdq2_reg       		  0x604		, 26		, 26		
 #define	 reg_b_l_abutnrcompdq1_reg       		  0x604		, 25		, 25		
 #define	 reg_b_l_abutnrcompdq0_reg       		  0x604		, 24		, 24		
 #define	 reg_b_l_abutprcompdq4_reg       		  0x604		, 20		, 20		
 #define	 reg_b_l_abutprcompdq3_reg       		  0x604		, 19		, 19		
 #define	 reg_b_l_abutprcompdq2_reg       		  0x604		, 18		, 18		
 #define	 reg_b_l_abutprcompdq1_reg       		  0x604		, 17		, 17		
 #define	 reg_b_l_abutprcompdq0_reg       		  0x604		, 16		, 16		
 #define	 reg_b_l_abutodtpddq4_reg        		  0x604		, 12		, 12		
 #define	 reg_b_l_abutodtpddq3_reg        		  0x604		, 11		, 11		
 #define	 reg_b_l_abutodtpddq2_reg        		  0x604		, 10		, 10		
 #define	 reg_b_l_abutodtpddq1_reg        		  0x604		, 9		, 9		
 #define	 reg_b_l_abutodtpddq0_reg        		  0x604		, 8		, 8		
 #define	 reg_b_l_abutodtpudq4_reg        		  0x604		, 4		, 4		
 #define	 reg_b_l_abutodtpudq3_reg        		  0x604		, 3		, 3		
 #define	 reg_b_l_abutodtpudq2_reg        		  0x604		, 2		, 2		
 #define	 reg_b_l_abutodtpudq1_reg        		  0x604		, 1		, 1		
 #define	 reg_b_l_abutodtpudq0_reg        		  0x604		, 0		, 0		
 #define	 reg_b_l_rxmen0_delay_bp         		  0x620		, 26		, 24		
 #define	 reg_b_l_rxmen0_ophsel_bp        		  0x620		, 23		, 21		
 #define	 reg_b_l_rxmen0_sdlltap_bp       		  0x620		, 20		, 15		
 #define	 reg_b_l_rxmen1_delay_bp         		  0x620		, 11		, 9		
 #define	 reg_b_l_rxmen1_ophsel_bp        		  0x620		, 8		, 6		
 #define	 reg_b_l_rxmen1_sdlltap_bp       		  0x620		, 5		, 0		
 #define	 reg_b_l_rdodt0_delay            		  0x624		, 26		, 24		
 #define	 reg_b_l_rdodt0_ophsel           		  0x624		, 23		, 21		
 #define	 reg_b_l_rdodt0_dllsel           		  0x624		, 20		, 16		
 #define	 reg_b_l_rdodt1_delay            		  0x624		, 10		, 8		
 #define	 reg_b_l_rdodt1_ophsel           		  0x624		, 7		, 5		
 #define	 reg_b_l_rdodt1_dllsel           		  0x624		, 4		, 0		
 #define	 reg_b_l_dm_obsdataen            		  0x628		, 28		, 28		
 #define	 reg_b_l_dqobsmuxsel             		  0x628		, 27		, 24		
 #define	 reg_b_l_dqout_mux               		  0x628		, 23		, 23		
 #define	 reg_b_l_dmout_mux               		  0x628		, 22		, 22		
 #define	 reg_b_l_dq_ph90en_bp            		  0x628		, 21		, 21		
 #define	 reg_b_l_dqs_ph90en_bp           		  0x628		, 20		, 20		
 #define	 reg_b_l_rcvdqsmodsel            		  0x628		, 19		, 19		
 #define	 reg_b_l_selfclren               		  0x628		, 18		, 18		
 #define	 reg_b_l_wrptrclrb               		  0x628		, 17		, 17		
 #define	 reg_b_l_rxm_odiffampen          		  0x628		, 16		, 16		
 #define	 reg_b_l_abutobsmodeen           		  0x628		, 15		, 15		
 #define	 reg_b_l_odtenb4p5en             		  0x628		, 14		, 14		
 #define	 reg_b_l_rxm4p5en                		  0x628		, 13		, 13		
 #define	 reg_b_l_tsm_iobufact_bp         		  0x628		, 12		, 12		
 #define	 reg_b_l_rxpst_bp                		  0x628		, 11		, 11		
 #define	 reg_b_l_odtenb4p5en_r2          		  0x628		, 10		, 10		
 #define	 reg_b_l_rxm4p5en_r2             		  0x628		, 9		, 9		
 #define	 reg_b_l_wrankphsel              		  0x628		, 8		, 6		
 #define	 reg_b_l_rrankdly_4x_cs0         		  0x628		, 5		, 3		
 #define	 reg_b_l_rrankdly_4x_cs1         		  0x628		, 2		, 0		
 #define	 reg_b_l_rrank_dlldly_cs0        		  0x62c		, 11		, 6		
 #define	 reg_b_l_rrank_dlldly_cs1        		  0x62c		, 5		, 0		
 #define	 reg_b_l_cs0_dm_invdelaysel      		  0x650		, 5		, 0		
 #define	 reg_b_l_cs0_dq0_invdelaysel     		  0x654		, 29		, 24		
 #define	 reg_b_l_cs0_dq1_invdelaysel     		  0x654		, 21		, 16		
 #define	 reg_b_l_cs0_dq2_invdelaysel     		  0x654		, 13		, 8		
 #define	 reg_b_l_cs0_dq3_invdelaysel     		  0x654		, 5		, 0		
 #define	 reg_b_l_cs0_dq4_invdelaysel     		  0x658		, 29		, 24		
 #define	 reg_b_l_cs0_dq5_invdelaysel     		  0x658		, 21		, 16		
 #define	 reg_b_l_cs0_dq6_invdelaysel     		  0x658		, 13		, 8		
 #define	 reg_b_l_cs0_dq7_invdelaysel     		  0x658		, 5		, 0		
 #define	 reg_b_l_cs0_dqs_invdelaysel     		  0x65c		, 29		, 24		
 #define	 reg_b_l_cs0_dqsb_invdelaysel    		  0x65c		, 13		, 8		
 #define	 reg_b_l_cs0_loop_invdelaysel    		  0x660		, 28		, 24		
 #define	 reg_b_l_cs0_dm_invdelayselrx    		  0x660		, 13		, 8		
 #define	 reg_b_l_cs0_dq0_invdelayselrx   		  0x664		, 29		, 24		
 #define	 reg_b_l_cs0_dq1_invdelayselrx   		  0x664		, 21		, 16		
 #define	 reg_b_l_cs0_dq2_invdelayselrx   		  0x664		, 13		, 8		
 #define	 reg_b_l_cs0_dq3_invdelayselrx   		  0x664		, 5		, 0		
 #define	 reg_b_l_cs0_dq4_invdelayselrx   		  0x668		, 29		, 24		
 #define	 reg_b_l_cs0_dq5_invdelayselrx   		  0x668		, 21		, 16		
 #define	 reg_b_l_cs0_dq6_invdelayselrx   		  0x668		, 13		, 8		
 #define	 reg_b_l_cs0_dq7_invdelayselrx   		  0x668		, 5		, 0		
 #define	 reg_b_l_cs0_dqs_invdelayselrx   		  0x66c		, 29		, 24		
 #define	 reg_b_l_cs0_dqsb_invdelayselrx  		  0x66c		, 13		, 8		
 #define	 reg_b_l_cs1_dm_invdelaysel      		  0x670		, 5		, 0		
 #define	 reg_b_l_cs1_dq0_invdelaysel     		  0x674		, 29		, 24		
 #define	 reg_b_l_cs1_dq1_invdelaysel     		  0x674		, 21		, 16		
 #define	 reg_b_l_cs1_dq2_invdelaysel     		  0x674		, 13		, 8		
 #define	 reg_b_l_cs1_dq3_invdelaysel     		  0x674		, 5		, 0		
 #define	 reg_b_l_cs1_dq4_invdelaysel     		  0x678		, 29		, 24		
 #define	 reg_b_l_cs1_dq5_invdelaysel     		  0x678		, 21		, 16		
 #define	 reg_b_l_cs1_dq6_invdelaysel     		  0x678		, 13		, 8		
 #define	 reg_b_l_cs1_dq7_invdelaysel     		  0x678		, 5		, 0		
 #define	 reg_b_l_cs1_dqs_invdelaysel     		  0x67c		, 29		, 24		
 #define	 reg_b_l_cs1_dqsb_invdelaysel    		  0x67c		, 13		, 8		
 #define	 reg_b_l_cs1_loop_invdelaysel    		  0x680		, 28		, 24		
 #define	 reg_b_l_cs1_dm_invdelayselrx    		  0x680		, 13		, 8		
 #define	 reg_b_l_cs1_dq0_invdelayselrx   		  0x684		, 29		, 24		
 #define	 reg_b_l_cs1_dq1_invdelayselrx   		  0x684		, 21		, 16		
 #define	 reg_b_l_cs1_dq2_invdelayselrx   		  0x684		, 13		, 8		
 #define	 reg_b_l_cs1_dq3_invdelayselrx   		  0x684		, 5		, 0		
 #define	 reg_b_l_cs1_dq4_invdelayselrx   		  0x688		, 29		, 24		
 #define	 reg_b_l_cs1_dq5_invdelayselrx   		  0x688		, 21		, 16		
 #define	 reg_b_l_cs1_dq6_invdelayselrx   		  0x688		, 13		, 8		
 #define	 reg_b_l_cs1_dq7_invdelayselrx   		  0x688		, 5		, 0		
 #define	 reg_b_l_cs1_dqs_invdelayselrx   		  0x68c		, 29		, 24		
 #define	 reg_b_l_cs1_dqsb_invdelayselrx  		  0x68c		, 13		, 8		
 #define	 reg_b_l_rd_train_dqs_default    		  0x6a0		, 29		, 24		
 #define	 reg_b_l_train_dqs_default       		  0x6a0		, 21		, 16		
 #define	 reg_b_l_rd_train_dqs_range_max  		  0x6a0		, 13		, 8		
 #define	 reg_b_l_rd_train_dqs_range_min  		  0x6a0		, 5		, 0		
 #define	 reg_b_l_rdtrain_check_wrap0     		  0x6a4		, 15		, 8		
 #define	 reg_b_l_rdtrain_check_wrap1     		  0x6a4		, 7		, 0		


// RO REGISTER LIST
 #define	 reg_b_l_dqs_idqshigh            		  0x6e0		, 30		, 30		
 #define	 reg_b_l_tdqs_invdelaysel0       		  0x6e0		, 21		, 16		
 #define	 reg_b_l_tdqs_invdelaysel1       		  0x6e0		, 5		, 0		
 #define	 reg_b_l_cycsel                  		  0x6e4		, 11		, 9		
 #define	 reg_b_l_ophsel                  		  0x6e4		, 8		, 6		
 #define	 reg_b_l_dllsel                  		  0x6e4		, 5		, 0		
 #define	 reg_b_l_calib_result_cs0        		  0x6e8		, 27		, 16		
 #define	 reg_b_l_calib_result_cs1        		  0x6e8		, 11		, 0		
 #define	 reg_b_l_cs0_value_dqx_invdelaysel		  0x6ec		, 13		, 8		
 #define	 reg_b_l_cs1_value_dqx_invdelaysel		  0x6f0		, 13		, 8		
 #define	 reg_b_l_train_min_for_rd_dq0    		  0x6f4		, 29		, 24		
 #define	 reg_b_l_train_min_for_rd_dq1    		  0x6f4		, 21		, 16		
 #define	 reg_b_l_train_min_for_rd_dq2    		  0x6f4		, 13		, 8		
 #define	 reg_b_l_train_min_for_rd_dq3    		  0x6f4		, 5		, 0		
 #define	 reg_b_l_train_min_for_rd_dq4    		  0x6f8		, 29		, 24		
 #define	 reg_b_l_train_min_for_rd_dq5    		  0x6f8		, 21		, 16		
 #define	 reg_b_l_train_min_for_rd_dq6    		  0x6f8		, 13		, 8		
 #define	 reg_b_l_train_min_for_rd_dq7    		  0x6f8		, 5		, 0		
 #define	 reg_b_l_train_min_for_rd_dqs    		  0x6fc		, 5		, 0		
 #define	 reg_b_l_train_max_for_rd_dq0    		  0x700		, 29		, 24		
 #define	 reg_b_l_train_max_for_rd_dq1    		  0x700		, 21		, 16		
 #define	 reg_b_l_train_max_for_rd_dq2    		  0x700		, 13		, 8		
 #define	 reg_b_l_train_max_for_rd_dq3    		  0x700		, 5		, 0		
 #define	 reg_b_l_train_max_for_rd_dq4    		  0x704		, 29		, 24		
 #define	 reg_b_l_train_max_for_rd_dq5    		  0x704		, 21		, 16		
 #define	 reg_b_l_train_max_for_rd_dq6    		  0x704		, 13		, 8		
 #define	 reg_b_l_train_max_for_rd_dq7    		  0x704		, 5		, 0		
 #define	 reg_b_l_train_max_for_rd_dqs    		  0x708		, 5		, 0		
 #define	 reg_b_l_train_result_for_rd_base_dqs		  0x70c		, 23		, 18		
 #define	 reg_b_l_change_rd_dqs_default   		  0x70c		, 5		, 5		
 #define	 reg_b_l_left_boundary_overflow_for_rd		  0x70c		, 3		, 3		
 #define	 reg_b_l_right_boundary_overflow_for_rd		  0x70c		, 2		, 2		
 #define	 reg_b_l_rd_train_readback_data_dq0		  0x710		, 31		, 16		
 #define	 reg_b_l_rd_train_readback_data_dq1		  0x710		, 15		, 0		
 #define	 reg_b_l_rd_train_readback_data_dq2		  0x714		, 31		, 16		
 #define	 reg_b_l_rd_train_readback_data_dq3		  0x714		, 15		, 0		
 #define	 reg_b_l_rd_train_readback_data_dq4		  0x718		, 31		, 16		
 #define	 reg_b_l_rd_train_readback_data_dq5		  0x718		, 15		, 0		
 #define	 reg_b_l_rd_train_readback_data_dq6		  0x71c		, 31		, 16		
 #define	 reg_b_l_rd_train_readback_data_dq7		  0x71c		, 15		, 0		
 #define	 reg_b_l_change_dqs_default      		  0x720		, 16		, 16		
 #define	 reg_b_l_train_min_for_dqs       		  0x720		, 5		, 0		
 #define	 reg_b_l_train_min_for_dq0       		  0x724		, 29		, 24		
 #define	 reg_b_l_train_min_for_dq1       		  0x724		, 21		, 16		
 #define	 reg_b_l_train_min_for_dq2       		  0x724		, 13		, 8		
 #define	 reg_b_l_train_min_for_dq3       		  0x724		, 5		, 0		
 #define	 reg_b_l_train_min_for_dq4       		  0x728		, 29		, 24		
 #define	 reg_b_l_train_min_for_dq5       		  0x728		, 21		, 16		
 #define	 reg_b_l_train_min_for_dq6       		  0x728		, 13		, 8		
 #define	 reg_b_l_train_min_for_dq7       		  0x728		, 5		, 0		
 #define	 reg_b_l_train_max_for_dqs       		  0x72c		, 5		, 0		
 #define	 reg_b_l_train_max_for_dq0       		  0x730		, 29		, 24		
 #define	 reg_b_l_train_max_for_dq1       		  0x730		, 21		, 16		
 #define	 reg_b_l_train_max_for_dq2       		  0x730		, 13		, 8		
 #define	 reg_b_l_train_max_for_dq3       		  0x730		, 5		, 0		
 #define	 reg_b_l_train_max_for_dq4       		  0x734		, 29		, 24		
 #define	 reg_b_l_train_max_for_dq5       		  0x734		, 21		, 16		
 #define	 reg_b_l_train_max_for_dq6       		  0x734		, 13		, 8		
 #define	 reg_b_l_train_max_for_dq7       		  0x734		, 5		, 0		
 #define	 reg_b_l_rdtrain_vref_max        		  0x738		, 15		, 8		
 #define	 reg_b_l_rdtrain_vref_min        		  0x738		, 7		, 0		



// RW REGISTER LIST

 #define	 reg_b_h_vref1_margsel_reg       		  0x780		, 31		, 24		
 #define	 reg_b_h_dq_odt_zqcali_en        		  0x780		, 22		, 22		
 #define	 reg_b_h_dq_drv_zqcali_en        		  0x780		, 21		, 21		
 #define	 reg_b_h_abutweakpddq_reg        		  0x780		, 20		, 20		
 #define	 reg_b_h_abutweakpubdq_reg       		  0x780		, 19		, 19		
 #define	 reg_b_h_abutdiffampseen_reg     		  0x780		, 18		, 18		
 #define	 reg_b_h_dqfben_reg              		  0x780		, 17		, 17		
 #define	 reg_b_h_dqfbsel_reg             		  0x780		, 16		, 16		
 #define	 reg_b_h_vref1_pd_reg            		  0x780		, 15		, 15		
 #define	 reg_b_h_weakpd_reg              		  0x780		, 14		, 14		
 #define	 reg_b_h_weakpub_reg             		  0x780		, 13		, 13		
 #define	 reg_b_h_abutslewpu_reg          		  0x780		, 12		, 8		
 #define	 reg_b_h_enb_lp4mode_reg         		  0x780		, 7		, 7		
 #define	 reg_b_h_dqsweakpd_reg           		  0x780		, 6		, 6		
 #define	 reg_b_h_dqsbweakpub_reg         		  0x780		, 5		, 5		
 #define	 reg_b_h_abutslewpd_reg          		  0x780		, 4		, 0		
 #define	 reg_b_h_abutnrcompdq4_reg       		  0x784		, 28		, 28		
 #define	 reg_b_h_abutnrcompdq3_reg       		  0x784		, 27		, 27		
 #define	 reg_b_h_abutnrcompdq2_reg       		  0x784		, 26		, 26		
 #define	 reg_b_h_abutnrcompdq1_reg       		  0x784		, 25		, 25		
 #define	 reg_b_h_abutnrcompdq0_reg       		  0x784		, 24		, 24		
 #define	 reg_b_h_abutprcompdq4_reg       		  0x784		, 20		, 20		
 #define	 reg_b_h_abutprcompdq3_reg       		  0x784		, 19		, 19		
 #define	 reg_b_h_abutprcompdq2_reg       		  0x784		, 18		, 18		
 #define	 reg_b_h_abutprcompdq1_reg       		  0x784		, 17		, 17		
 #define	 reg_b_h_abutprcompdq0_reg       		  0x784		, 16		, 16		
 #define	 reg_b_h_abutodtpddq4_reg        		  0x784		, 12		, 12		
 #define	 reg_b_h_abutodtpddq3_reg        		  0x784		, 11		, 11		
 #define	 reg_b_h_abutodtpddq2_reg        		  0x784		, 10		, 10		
 #define	 reg_b_h_abutodtpddq1_reg        		  0x784		, 9		, 9		
 #define	 reg_b_h_abutodtpddq0_reg        		  0x784		, 8		, 8		
 #define	 reg_b_h_abutodtpudq4_reg        		  0x784		, 4		, 4		
 #define	 reg_b_h_abutodtpudq3_reg        		  0x784		, 3		, 3		
 #define	 reg_b_h_abutodtpudq2_reg        		  0x784		, 2		, 2		
 #define	 reg_b_h_abutodtpudq1_reg        		  0x784		, 1		, 1		
 #define	 reg_b_h_abutodtpudq0_reg        		  0x784		, 0		, 0		
 #define	 reg_b_h_rxmen0_delay_bp         		  0x7a0		, 26		, 24		
 #define	 reg_b_h_rxmen0_ophsel_bp        		  0x7a0		, 23		, 21		
 #define	 reg_b_h_rxmen0_sdlltap_bp       		  0x7a0		, 20		, 15		
 #define	 reg_b_h_rxmen1_delay_bp         		  0x7a0		, 11		, 9		
 #define	 reg_b_h_rxmen1_ophsel_bp        		  0x7a0		, 8		, 6		
 #define	 reg_b_h_rxmen1_sdlltap_bp       		  0x7a0		, 5		, 0		
 #define	 reg_b_h_rdodt0_delay            		  0x7a4		, 26		, 24		
 #define	 reg_b_h_rdodt0_ophsel           		  0x7a4		, 23		, 21		
 #define	 reg_b_h_rdodt0_dllsel           		  0x7a4		, 20		, 16		
 #define	 reg_b_h_rdodt1_delay            		  0x7a4		, 10		, 8		
 #define	 reg_b_h_rdodt1_ophsel           		  0x7a4		, 7		, 5		
 #define	 reg_b_h_rdodt1_dllsel           		  0x7a4		, 4		, 0		
 #define	 reg_b_h_dm_obsdataen            		  0x7a8		, 28		, 28		
 #define	 reg_b_h_dqobsmuxsel             		  0x7a8		, 27		, 24		
 #define	 reg_b_h_dqout_mux               		  0x7a8		, 23		, 23		
 #define	 reg_b_h_dmout_mux               		  0x7a8		, 22		, 22		
 #define	 reg_b_h_dq_ph90en_bp            		  0x7a8		, 21		, 21		
 #define	 reg_b_h_dqs_ph90en_bp           		  0x7a8		, 20		, 20		
 #define	 reg_b_h_rcvdqsmodsel            		  0x7a8		, 19		, 19		
 #define	 reg_b_h_selfclren               		  0x7a8		, 18		, 18		
 #define	 reg_b_h_wrptrclrb               		  0x7a8		, 17		, 17		
 #define	 reg_b_h_rxm_odiffampen          		  0x7a8		, 16		, 16		
 #define	 reg_b_h_abutobsmodeen           		  0x7a8		, 15		, 15		
 #define	 reg_b_h_odtenb4p5en             		  0x7a8		, 14		, 14		
 #define	 reg_b_h_rxm4p5en                		  0x7a8		, 13		, 13		
 #define	 reg_b_h_tsm_iobufact_bp         		  0x7a8		, 12		, 12		
 #define	 reg_b_h_rxpst_bp                		  0x7a8		, 11		, 11		
 #define	 reg_b_h_odtenb4p5en_r2          		  0x7a8		, 10		, 10		
 #define	 reg_b_h_rxm4p5en_r2             		  0x7a8		, 9		, 9		
 #define	 reg_b_h_wrankphsel              		  0x7a8		, 8		, 6		
 #define	 reg_b_h_rrankdly_4x_cs0         		  0x7a8		, 5		, 3		
 #define	 reg_b_h_rrankdly_4x_cs1         		  0x7a8		, 2		, 0		
 #define	 reg_b_h_rrank_dlldly_cs0        		  0x7ac		, 11		, 6		
 #define	 reg_b_h_rrank_dlldly_cs1        		  0x7ac		, 5		, 0		
 #define	 reg_b_h_cs0_dm_invdelaysel      		  0x7d0		, 5		, 0		
 #define	 reg_b_h_cs0_dq0_invdelaysel     		  0x7d4		, 29		, 24		
 #define	 reg_b_h_cs0_dq1_invdelaysel     		  0x7d4		, 21		, 16		
 #define	 reg_b_h_cs0_dq2_invdelaysel     		  0x7d4		, 13		, 8		
 #define	 reg_b_h_cs0_dq3_invdelaysel     		  0x7d4		, 5		, 0		
 #define	 reg_b_h_cs0_dq4_invdelaysel     		  0x7d8		, 29		, 24		
 #define	 reg_b_h_cs0_dq5_invdelaysel     		  0x7d8		, 21		, 16		
 #define	 reg_b_h_cs0_dq6_invdelaysel     		  0x7d8		, 13		, 8		
 #define	 reg_b_h_cs0_dq7_invdelaysel     		  0x7d8		, 5		, 0		
 #define	 reg_b_h_cs0_dqs_invdelaysel     		  0x7dc		, 29		, 24		
 #define	 reg_b_h_cs0_dqsb_invdelaysel    		  0x7dc		, 13		, 8		
 #define	 reg_b_h_cs0_loop_invdelaysel    		  0x7e0		, 28		, 24		
 #define	 reg_b_h_cs0_dm_invdelayselrx    		  0x7e0		, 13		, 8		
 #define	 reg_b_h_cs0_dq0_invdelayselrx   		  0x7e4		, 29		, 24		
 #define	 reg_b_h_cs0_dq1_invdelayselrx   		  0x7e4		, 21		, 16		
 #define	 reg_b_h_cs0_dq2_invdelayselrx   		  0x7e4		, 13		, 8		
 #define	 reg_b_h_cs0_dq3_invdelayselrx   		  0x7e4		, 5		, 0		
 #define	 reg_b_h_cs0_dq4_invdelayselrx   		  0x7e8		, 29		, 24		
 #define	 reg_b_h_cs0_dq5_invdelayselrx   		  0x7e8		, 21		, 16		
 #define	 reg_b_h_cs0_dq6_invdelayselrx   		  0x7e8		, 13		, 8		
 #define	 reg_b_h_cs0_dq7_invdelayselrx   		  0x7e8		, 5		, 0		
 #define	 reg_b_h_cs0_dqs_invdelayselrx   		  0x7ec		, 29		, 24		
 #define	 reg_b_h_cs0_dqsb_invdelayselrx  		  0x7ec		, 13		, 8		
 #define	 reg_b_h_cs1_dm_invdelaysel      		  0x7f0		, 5		, 0		
 #define	 reg_b_h_cs1_dq0_invdelaysel     		  0x7f4		, 29		, 24		
 #define	 reg_b_h_cs1_dq1_invdelaysel     		  0x7f4		, 21		, 16		
 #define	 reg_b_h_cs1_dq2_invdelaysel     		  0x7f4		, 13		, 8		
 #define	 reg_b_h_cs1_dq3_invdelaysel     		  0x7f4		, 5		, 0		
 #define	 reg_b_h_cs1_dq4_invdelaysel     		  0x7f8		, 29		, 24		
 #define	 reg_b_h_cs1_dq5_invdelaysel     		  0x7f8		, 21		, 16		
 #define	 reg_b_h_cs1_dq6_invdelaysel     		  0x7f8		, 13		, 8		
 #define	 reg_b_h_cs1_dq7_invdelaysel     		  0x7f8		, 5		, 0		
 #define	 reg_b_h_cs1_dqs_invdelaysel     		  0x7fc		, 29		, 24		
 #define	 reg_b_h_cs1_dqsb_invdelaysel    		  0x7fc		, 13		, 8		
 #define	 reg_b_h_cs1_loop_invdelaysel    		  0x800		, 28		, 24		
 #define	 reg_b_h_cs1_dm_invdelayselrx    		  0x800		, 13		, 8		
 #define	 reg_b_h_cs1_dq0_invdelayselrx   		  0x804		, 29		, 24		
 #define	 reg_b_h_cs1_dq1_invdelayselrx   		  0x804		, 21		, 16		
 #define	 reg_b_h_cs1_dq2_invdelayselrx   		  0x804		, 13		, 8		
 #define	 reg_b_h_cs1_dq3_invdelayselrx   		  0x804		, 5		, 0		
 #define	 reg_b_h_cs1_dq4_invdelayselrx   		  0x808		, 29		, 24		
 #define	 reg_b_h_cs1_dq5_invdelayselrx   		  0x808		, 21		, 16		
 #define	 reg_b_h_cs1_dq6_invdelayselrx   		  0x808		, 13		, 8		
 #define	 reg_b_h_cs1_dq7_invdelayselrx   		  0x808		, 5		, 0		
 #define	 reg_b_h_cs1_dqs_invdelayselrx   		  0x80c		, 29		, 24		
 #define	 reg_b_h_cs1_dqsb_invdelayselrx  		  0x80c		, 13		, 8		
 #define	 reg_b_h_rd_train_dqs_default    		  0x820		, 29		, 24		
 #define	 reg_b_h_train_dqs_default       		  0x820		, 21		, 16		
 #define	 reg_b_h_rd_train_dqs_range_max  		  0x820		, 13		, 8		
 #define	 reg_b_h_rd_train_dqs_range_min  		  0x820		, 5		, 0		
 #define	 reg_b_h_rdtrain_check_wrap0     		  0x824		, 15		, 8		
 #define	 reg_b_h_rdtrain_check_wrap1     		  0x824		, 7		, 0		


// RO REGISTER LIST
 #define	 reg_b_h_dqs_idqshigh            		  0x860		, 30		, 30		
 #define	 reg_b_h_tdqs_invdelaysel0       		  0x860		, 21		, 16		
 #define	 reg_b_h_tdqs_invdelaysel1       		  0x860		, 5		, 0		
 #define	 reg_b_h_cycsel                  		  0x864		, 11		, 9		
 #define	 reg_b_h_ophsel                  		  0x864		, 8		, 6		
 #define	 reg_b_h_dllsel                  		  0x864		, 5		, 0		
 #define	 reg_b_h_calib_result_cs0        		  0x868		, 27		, 16		
 #define	 reg_b_h_calib_result_cs1        		  0x868		, 11		, 0		
 #define	 reg_b_h_cs0_value_dqx_invdelaysel		  0x86c		, 13		, 8		
 #define	 reg_b_h_cs1_value_dqx_invdelaysel		  0x870		, 13		, 8		
 #define	 reg_b_h_train_min_for_rd_dq0    		  0x874		, 29		, 24		
 #define	 reg_b_h_train_min_for_rd_dq1    		  0x874		, 21		, 16		
 #define	 reg_b_h_train_min_for_rd_dq2    		  0x874		, 13		, 8		
 #define	 reg_b_h_train_min_for_rd_dq3    		  0x874		, 5		, 0		
 #define	 reg_b_h_train_min_for_rd_dq4    		  0x878		, 29		, 24		
 #define	 reg_b_h_train_min_for_rd_dq5    		  0x878		, 21		, 16		
 #define	 reg_b_h_train_min_for_rd_dq6    		  0x878		, 13		, 8		
 #define	 reg_b_h_train_min_for_rd_dq7    		  0x878		, 5		, 0		
 #define	 reg_b_h_train_min_for_rd_dqs    		  0x87c		, 5		, 0		
 #define	 reg_b_h_train_max_for_rd_dq0    		  0x880		, 29		, 24		
 #define	 reg_b_h_train_max_for_rd_dq1    		  0x880		, 21		, 16		
 #define	 reg_b_h_train_max_for_rd_dq2    		  0x880		, 13		, 8		
 #define	 reg_b_h_train_max_for_rd_dq3    		  0x880		, 5		, 0		
 #define	 reg_b_h_train_max_for_rd_dq4    		  0x884		, 29		, 24		
 #define	 reg_b_h_train_max_for_rd_dq5    		  0x884		, 21		, 16		
 #define	 reg_b_h_train_max_for_rd_dq6    		  0x884		, 13		, 8		
 #define	 reg_b_h_train_max_for_rd_dq7    		  0x884		, 5		, 0		
 #define	 reg_b_h_train_max_for_rd_dqs    		  0x888		, 5		, 0		
 #define	 reg_b_h_train_result_for_rd_base_dqs		  0x88c		, 23		, 18		
 #define	 reg_b_h_change_rd_dqs_default   		  0x88c		, 5		, 5		
 #define	 reg_b_h_left_boundary_overflow_for_rd		  0x88c		, 3		, 3		
 #define	 reg_b_h_right_boundary_overflow_for_rd		  0x88c		, 2		, 2		
 #define	 reg_b_h_rd_train_readback_data_dq0		  0x890		, 31		, 16		
 #define	 reg_b_h_rd_train_readback_data_dq1		  0x890		, 15		, 0		
 #define	 reg_b_h_rd_train_readback_data_dq2		  0x894		, 31		, 16		
 #define	 reg_b_h_rd_train_readback_data_dq3		  0x894		, 15		, 0		
 #define	 reg_b_h_rd_train_readback_data_dq4		  0x898		, 31		, 16		
 #define	 reg_b_h_rd_train_readback_data_dq5		  0x898		, 15		, 0		
 #define	 reg_b_h_rd_train_readback_data_dq6		  0x89c		, 31		, 16		
 #define	 reg_b_h_rd_train_readback_data_dq7		  0x89c		, 15		, 0		
 #define	 reg_b_h_change_dqs_default      		  0x8a0		, 16		, 16		
 #define	 reg_b_h_train_min_for_dqs       		  0x8a0		, 5		, 0		
 #define	 reg_b_h_train_min_for_dq0       		  0x8a4		, 29		, 24		
 #define	 reg_b_h_train_min_for_dq1       		  0x8a4		, 21		, 16		
 #define	 reg_b_h_train_min_for_dq2       		  0x8a4		, 13		, 8		
 #define	 reg_b_h_train_min_for_dq3       		  0x8a4		, 5		, 0		
 #define	 reg_b_h_train_min_for_dq4       		  0x8a8		, 29		, 24		
 #define	 reg_b_h_train_min_for_dq5       		  0x8a8		, 21		, 16		
 #define	 reg_b_h_train_min_for_dq6       		  0x8a8		, 13		, 8		
 #define	 reg_b_h_train_min_for_dq7       		  0x8a8		, 5		, 0		
 #define	 reg_b_h_train_max_for_dqs       		  0x8ac		, 5		, 0		
 #define	 reg_b_h_train_max_for_dq0       		  0x8b0		, 29		, 24		
 #define	 reg_b_h_train_max_for_dq1       		  0x8b0		, 21		, 16		
 #define	 reg_b_h_train_max_for_dq2       		  0x8b0		, 13		, 8		
 #define	 reg_b_h_train_max_for_dq3       		  0x8b0		, 5		, 0		
 #define	 reg_b_h_train_max_for_dq4       		  0x8b4		, 29		, 24		
 #define	 reg_b_h_train_max_for_dq5       		  0x8b4		, 21		, 16		
 #define	 reg_b_h_train_max_for_dq6       		  0x8b4		, 13		, 8		
 #define	 reg_b_h_train_max_for_dq7       		  0x8b4		, 5		, 0		
 #define	 reg_b_h_rdtrain_vref_max        		  0x8b8		, 15		, 8		
 #define	 reg_b_h_rdtrain_vref_min        		  0x8b8		, 7		, 0		



// RW REGISTER LIST

 #define	 reg_a_l_vref1_margsel_reg       		  0x300		, 31		, 24		
 #define	 reg_a_l_dq_odt_zqcali_en        		  0x300		, 22		, 22		
 #define	 reg_a_l_dq_drv_zqcali_en        		  0x300		, 21		, 21		
 #define	 reg_a_l_abutweakpddq_reg        		  0x300		, 20		, 20		
 #define	 reg_a_l_abutweakpubdq_reg       		  0x300		, 19		, 19		
 #define	 reg_a_l_abutdiffampseen_reg     		  0x300		, 18		, 18		
 #define	 reg_a_l_dqfben_reg              		  0x300		, 17		, 17		
 #define	 reg_a_l_dqfbsel_reg             		  0x300		, 16		, 16		
 #define	 reg_a_l_vref1_pd_reg            		  0x300		, 15		, 15		
 #define	 reg_a_l_weakpd_reg              		  0x300		, 14		, 14		
 #define	 reg_a_l_weakpub_reg             		  0x300		, 13		, 13		
 #define	 reg_a_l_abutslewpu_reg          		  0x300		, 12		, 8		
 #define	 reg_a_l_enb_lp4mode_reg         		  0x300		, 7		, 7		
 #define	 reg_a_l_dqsweakpd_reg           		  0x300		, 6		, 6		
 #define	 reg_a_l_dqsbweakpub_reg         		  0x300		, 5		, 5		
 #define	 reg_a_l_abutslewpd_reg          		  0x300		, 4		, 0		
 #define	 reg_a_l_abutnrcompdq4_reg       		  0x304		, 28		, 28		
 #define	 reg_a_l_abutnrcompdq3_reg       		  0x304		, 27		, 27		
 #define	 reg_a_l_abutnrcompdq2_reg       		  0x304		, 26		, 26		
 #define	 reg_a_l_abutnrcompdq1_reg       		  0x304		, 25		, 25		
 #define	 reg_a_l_abutnrcompdq0_reg       		  0x304		, 24		, 24		
 #define	 reg_a_l_abutprcompdq4_reg       		  0x304		, 20		, 20		
 #define	 reg_a_l_abutprcompdq3_reg       		  0x304		, 19		, 19		
 #define	 reg_a_l_abutprcompdq2_reg       		  0x304		, 18		, 18		
 #define	 reg_a_l_abutprcompdq1_reg       		  0x304		, 17		, 17		
 #define	 reg_a_l_abutprcompdq0_reg       		  0x304		, 16		, 16		
 #define	 reg_a_l_abutodtpddq4_reg        		  0x304		, 12		, 12		
 #define	 reg_a_l_abutodtpddq3_reg        		  0x304		, 11		, 11		
 #define	 reg_a_l_abutodtpddq2_reg        		  0x304		, 10		, 10		
 #define	 reg_a_l_abutodtpddq1_reg        		  0x304		, 9		, 9		
 #define	 reg_a_l_abutodtpddq0_reg        		  0x304		, 8		, 8		
 #define	 reg_a_l_abutodtpudq4_reg        		  0x304		, 4		, 4		
 #define	 reg_a_l_abutodtpudq3_reg        		  0x304		, 3		, 3		
 #define	 reg_a_l_abutodtpudq2_reg        		  0x304		, 2		, 2		
 #define	 reg_a_l_abutodtpudq1_reg        		  0x304		, 1		, 1		
 #define	 reg_a_l_abutodtpudq0_reg        		  0x304		, 0		, 0		
 #define	 reg_a_l_rxmen0_delay_bp         		  0x320		, 26		, 24		
 #define	 reg_a_l_rxmen0_ophsel_bp        		  0x320		, 23		, 21		
 #define	 reg_a_l_rxmen0_sdlltap_bp       		  0x320		, 20		, 15		
 #define	 reg_a_l_rxmen1_delay_bp         		  0x320		, 11		, 9		
 #define	 reg_a_l_rxmen1_ophsel_bp        		  0x320		, 8		, 6		
 #define	 reg_a_l_rxmen1_sdlltap_bp       		  0x320		, 5		, 0		
 #define	 reg_a_l_rdodt0_delay            		  0x324		, 26		, 24		
 #define	 reg_a_l_rdodt0_ophsel           		  0x324		, 23		, 21		
 #define	 reg_a_l_rdodt0_dllsel           		  0x324		, 20		, 16		
 #define	 reg_a_l_rdodt1_delay            		  0x324		, 10		, 8		
 #define	 reg_a_l_rdodt1_ophsel           		  0x324		, 7		, 5		
 #define	 reg_a_l_rdodt1_dllsel           		  0x324		, 4		, 0		
 #define	 reg_a_l_dm_obsdataen            		  0x328		, 28		, 28		
 #define	 reg_a_l_dqobsmuxsel             		  0x328		, 27		, 24		
 #define	 reg_a_l_dqout_mux               		  0x328		, 23		, 23		
 #define	 reg_a_l_dmout_mux               		  0x328		, 22		, 22		
 #define	 reg_a_l_dq_ph90en_bp            		  0x328		, 21		, 21		
 #define	 reg_a_l_dqs_ph90en_bp           		  0x328		, 20		, 20		
 #define	 reg_a_l_rcvdqsmodsel            		  0x328		, 19		, 19		
 #define	 reg_a_l_selfclren               		  0x328		, 18		, 18		
 #define	 reg_a_l_wrptrclrb               		  0x328		, 17		, 17		
 #define	 reg_a_l_rxm_odiffampen          		  0x328		, 16		, 16		
 #define	 reg_a_l_abutobsmodeen           		  0x328		, 15		, 15		
 #define	 reg_a_l_odtenb4p5en             		  0x328		, 14		, 14		
 #define	 reg_a_l_rxm4p5en                		  0x328		, 13		, 13		
 #define	 reg_a_l_tsm_iobufact_bp         		  0x328		, 12		, 12		
 #define	 reg_a_l_rxpst_bp                		  0x328		, 11		, 11		
 #define	 reg_a_l_odtenb4p5en_r2          		  0x328		, 10		, 10		
 #define	 reg_a_l_rxm4p5en_r2             		  0x328		, 9		, 9		
 #define	 reg_a_l_wrankphsel              		  0x328		, 8		, 6		
 #define	 reg_a_l_rrankdly_4x_cs0         		  0x328		, 5		, 3		
 #define	 reg_a_l_rrankdly_4x_cs1         		  0x328		, 2		, 0		
 #define	 reg_a_l_rrank_dlldly_cs0        		  0x32c		, 11		, 6		
 #define	 reg_a_l_rrank_dlldly_cs1        		  0x32c		, 5		, 0		
 #define	 reg_a_l_cs0_dm_invdelaysel      		  0x350		, 5		, 0		
 #define	 reg_a_l_cs0_dq0_invdelaysel     		  0x354		, 29		, 24		
 #define	 reg_a_l_cs0_dq1_invdelaysel     		  0x354		, 21		, 16		
 #define	 reg_a_l_cs0_dq2_invdelaysel     		  0x354		, 13		, 8		
 #define	 reg_a_l_cs0_dq3_invdelaysel     		  0x354		, 5		, 0		
 #define	 reg_a_l_cs0_dq4_invdelaysel     		  0x358		, 29		, 24		
 #define	 reg_a_l_cs0_dq5_invdelaysel     		  0x358		, 21		, 16		
 #define	 reg_a_l_cs0_dq6_invdelaysel     		  0x358		, 13		, 8		
 #define	 reg_a_l_cs0_dq7_invdelaysel     		  0x358		, 5		, 0		
 #define	 reg_a_l_cs0_dqs_invdelaysel     		  0x35c		, 29		, 24		
 #define	 reg_a_l_cs0_dqsb_invdelaysel    		  0x35c		, 13		, 8		
 #define	 reg_a_l_cs0_loop_invdelaysel    		  0x360		, 28		, 24		
 #define	 reg_a_l_cs0_dm_invdelayselrx    		  0x360		, 13		, 8		
 #define	 reg_a_l_cs0_dq0_invdelayselrx   		  0x364		, 29		, 24		
 #define	 reg_a_l_cs0_dq1_invdelayselrx   		  0x364		, 21		, 16		
 #define	 reg_a_l_cs0_dq2_invdelayselrx   		  0x364		, 13		, 8		
 #define	 reg_a_l_cs0_dq3_invdelayselrx   		  0x364		, 5		, 0		
 #define	 reg_a_l_cs0_dq4_invdelayselrx   		  0x368		, 29		, 24		
 #define	 reg_a_l_cs0_dq5_invdelayselrx   		  0x368		, 21		, 16		
 #define	 reg_a_l_cs0_dq6_invdelayselrx   		  0x368		, 13		, 8		
 #define	 reg_a_l_cs0_dq7_invdelayselrx   		  0x368		, 5		, 0		
 #define	 reg_a_l_cs0_dqs_invdelayselrx   		  0x36c		, 29		, 24		
 #define	 reg_a_l_cs0_dqsb_invdelayselrx  		  0x36c		, 13		, 8		
 #define	 reg_a_l_cs1_dm_invdelaysel      		  0x370		, 5		, 0		
 #define	 reg_a_l_cs1_dq0_invdelaysel     		  0x374		, 29		, 24		
 #define	 reg_a_l_cs1_dq1_invdelaysel     		  0x374		, 21		, 16		
 #define	 reg_a_l_cs1_dq2_invdelaysel     		  0x374		, 13		, 8		
 #define	 reg_a_l_cs1_dq3_invdelaysel     		  0x374		, 5		, 0		
 #define	 reg_a_l_cs1_dq4_invdelaysel     		  0x378		, 29		, 24		
 #define	 reg_a_l_cs1_dq5_invdelaysel     		  0x378		, 21		, 16		
 #define	 reg_a_l_cs1_dq6_invdelaysel     		  0x378		, 13		, 8		
 #define	 reg_a_l_cs1_dq7_invdelaysel     		  0x378		, 5		, 0		
 #define	 reg_a_l_cs1_dqs_invdelaysel     		  0x37c		, 29		, 24		
 #define	 reg_a_l_cs1_dqsb_invdelaysel    		  0x37c		, 13		, 8		
 #define	 reg_a_l_cs1_loop_invdelaysel    		  0x380		, 28		, 24		
 #define	 reg_a_l_cs1_dm_invdelayselrx    		  0x380		, 13		, 8		
 #define	 reg_a_l_cs1_dq0_invdelayselrx   		  0x384		, 29		, 24		
 #define	 reg_a_l_cs1_dq1_invdelayselrx   		  0x384		, 21		, 16		
 #define	 reg_a_l_cs1_dq2_invdelayselrx   		  0x384		, 13		, 8		
 #define	 reg_a_l_cs1_dq3_invdelayselrx   		  0x384		, 5		, 0		
 #define	 reg_a_l_cs1_dq4_invdelayselrx   		  0x388		, 29		, 24		
 #define	 reg_a_l_cs1_dq5_invdelayselrx   		  0x388		, 21		, 16		
 #define	 reg_a_l_cs1_dq6_invdelayselrx   		  0x388		, 13		, 8		
 #define	 reg_a_l_cs1_dq7_invdelayselrx   		  0x388		, 5		, 0		
 #define	 reg_a_l_cs1_dqs_invdelayselrx   		  0x38c		, 29		, 24		
 #define	 reg_a_l_cs1_dqsb_invdelayselrx  		  0x38c		, 13		, 8		
 #define	 reg_a_l_rd_train_dqs_default    		  0x3a0		, 29		, 24		
 #define	 reg_a_l_train_dqs_default       		  0x3a0		, 21		, 16		
 #define	 reg_a_l_rd_train_dqs_range_max  		  0x3a0		, 13		, 8		
 #define	 reg_a_l_rd_train_dqs_range_min  		  0x3a0		, 5		, 0		
 #define	 reg_a_l_rdtrain_check_wrap0     		  0x3a4		, 15		, 8		
 #define	 reg_a_l_rdtrain_check_wrap1     		  0x3a4		, 7		, 0		


// RO REGISTER LIST
 #define	 reg_a_l_dqs_idqshigh            		  0x3e0		, 30		, 30		
 #define	 reg_a_l_tdqs_invdelaysel0       		  0x3e0		, 21		, 16		
 #define	 reg_a_l_tdqs_invdelaysel1       		  0x3e0		, 5		, 0		
 #define	 reg_a_l_cycsel                  		  0x3e4		, 11		, 9		
 #define	 reg_a_l_ophsel                  		  0x3e4		, 8		, 6		
 #define	 reg_a_l_dllsel                  		  0x3e4		, 5		, 0		
 #define	 reg_a_l_calib_result_cs0        		  0x3e8		, 27		, 16		
 #define	 reg_a_l_calib_result_cs1        		  0x3e8		, 11		, 0		
 #define	 reg_a_l_cs0_value_dqx_invdelaysel		  0x3ec		, 13		, 8		
 #define	 reg_a_l_cs1_value_dqx_invdelaysel		  0x3f0		, 13		, 8		
 #define	 reg_a_l_train_min_for_rd_dq0    		  0x3f4		, 29		, 24		
 #define	 reg_a_l_train_min_for_rd_dq1    		  0x3f4		, 21		, 16		
 #define	 reg_a_l_train_min_for_rd_dq2    		  0x3f4		, 13		, 8		
 #define	 reg_a_l_train_min_for_rd_dq3    		  0x3f4		, 5		, 0		
 #define	 reg_a_l_train_min_for_rd_dq4    		  0x3f8		, 29		, 24		
 #define	 reg_a_l_train_min_for_rd_dq5    		  0x3f8		, 21		, 16		
 #define	 reg_a_l_train_min_for_rd_dq6    		  0x3f8		, 13		, 8		
 #define	 reg_a_l_train_min_for_rd_dq7    		  0x3f8		, 5		, 0		
 #define	 reg_a_l_train_min_for_rd_dqs    		  0x3fc		, 5		, 0		
 #define	 reg_a_l_train_max_for_rd_dq0    		  0x400		, 29		, 24		
 #define	 reg_a_l_train_max_for_rd_dq1    		  0x400		, 21		, 16		
 #define	 reg_a_l_train_max_for_rd_dq2    		  0x400		, 13		, 8		
 #define	 reg_a_l_train_max_for_rd_dq3    		  0x400		, 5		, 0		
 #define	 reg_a_l_train_max_for_rd_dq4    		  0x404		, 29		, 24		
 #define	 reg_a_l_train_max_for_rd_dq5    		  0x404		, 21		, 16		
 #define	 reg_a_l_train_max_for_rd_dq6    		  0x404		, 13		, 8		
 #define	 reg_a_l_train_max_for_rd_dq7    		  0x404		, 5		, 0		
 #define	 reg_a_l_train_max_for_rd_dqs    		  0x408		, 5		, 0		
 #define	 reg_a_l_train_result_for_rd_base_dqs		  0x40c		, 23		, 18		
 #define	 reg_a_l_change_rd_dqs_default   		  0x40c		, 5		, 5		
 #define	 reg_a_l_left_boundary_overflow_for_rd		  0x40c		, 3		, 3		
 #define	 reg_a_l_right_boundary_overflow_for_rd		  0x40c		, 2		, 2		
 #define	 reg_a_l_rd_train_readback_data_dq0		  0x410		, 31		, 16		
 #define	 reg_a_l_rd_train_readback_data_dq1		  0x410		, 15		, 0		
 #define	 reg_a_l_rd_train_readback_data_dq2		  0x414		, 31		, 16		
 #define	 reg_a_l_rd_train_readback_data_dq3		  0x414		, 15		, 0		
 #define	 reg_a_l_rd_train_readback_data_dq4		  0x418		, 31		, 16		
 #define	 reg_a_l_rd_train_readback_data_dq5		  0x418		, 15		, 0		
 #define	 reg_a_l_rd_train_readback_data_dq6		  0x41c		, 31		, 16		
 #define	 reg_a_l_rd_train_readback_data_dq7		  0x41c		, 15		, 0		
 #define	 reg_a_l_change_dqs_default      		  0x420		, 16		, 16		
 #define	 reg_a_l_train_min_for_dqs       		  0x420		, 5		, 0		
 #define	 reg_a_l_train_min_for_dq0       		  0x424		, 29		, 24		
 #define	 reg_a_l_train_min_for_dq1       		  0x424		, 21		, 16		
 #define	 reg_a_l_train_min_for_dq2       		  0x424		, 13		, 8		
 #define	 reg_a_l_train_min_for_dq3       		  0x424		, 5		, 0		
 #define	 reg_a_l_train_min_for_dq4       		  0x428		, 29		, 24		
 #define	 reg_a_l_train_min_for_dq5       		  0x428		, 21		, 16		
 #define	 reg_a_l_train_min_for_dq6       		  0x428		, 13		, 8		
 #define	 reg_a_l_train_min_for_dq7       		  0x428		, 5		, 0		
 #define	 reg_a_l_train_max_for_dqs       		  0x42c		, 5		, 0		
 #define	 reg_a_l_train_max_for_dq0       		  0x430		, 29		, 24		
 #define	 reg_a_l_train_max_for_dq1       		  0x430		, 21		, 16		
 #define	 reg_a_l_train_max_for_dq2       		  0x430		, 13		, 8		
 #define	 reg_a_l_train_max_for_dq3       		  0x430		, 5		, 0		
 #define	 reg_a_l_train_max_for_dq4       		  0x434		, 29		, 24		
 #define	 reg_a_l_train_max_for_dq5       		  0x434		, 21		, 16		
 #define	 reg_a_l_train_max_for_dq6       		  0x434		, 13		, 8		
 #define	 reg_a_l_train_max_for_dq7       		  0x434		, 5		, 0		
 #define	 reg_a_l_rdtrain_vref_max        		  0x438		, 15		, 8		
 #define	 reg_a_l_rdtrain_vref_min        		  0x438		, 7		, 0		



// RW REGISTER LIST

 #define	 reg_a_h_vref1_margsel_reg       		  0x480		, 31		, 24		
 #define	 reg_a_h_dq_odt_zqcali_en        		  0x480		, 22		, 22		
 #define	 reg_a_h_dq_drv_zqcali_en        		  0x480		, 21		, 21		
 #define	 reg_a_h_abutweakpddq_reg        		  0x480		, 20		, 20		
 #define	 reg_a_h_abutweakpubdq_reg       		  0x480		, 19		, 19		
 #define	 reg_a_h_abutdiffampseen_reg     		  0x480		, 18		, 18		
 #define	 reg_a_h_dqfben_reg              		  0x480		, 17		, 17		
 #define	 reg_a_h_dqfbsel_reg             		  0x480		, 16		, 16		
 #define	 reg_a_h_vref1_pd_reg            		  0x480		, 15		, 15		
 #define	 reg_a_h_weakpd_reg              		  0x480		, 14		, 14		
 #define	 reg_a_h_weakpub_reg             		  0x480		, 13		, 13		
 #define	 reg_a_h_abutslewpu_reg          		  0x480		, 12		, 8		
 #define	 reg_a_h_enb_lp4mode_reg         		  0x480		, 7		, 7		
 #define	 reg_a_h_dqsweakpd_reg           		  0x480		, 6		, 6		
 #define	 reg_a_h_dqsbweakpub_reg         		  0x480		, 5		, 5		
 #define	 reg_a_h_abutslewpd_reg          		  0x480		, 4		, 0		
 #define	 reg_a_h_abutnrcompdq4_reg       		  0x484		, 28		, 28		
 #define	 reg_a_h_abutnrcompdq3_reg       		  0x484		, 27		, 27		
 #define	 reg_a_h_abutnrcompdq2_reg       		  0x484		, 26		, 26		
 #define	 reg_a_h_abutnrcompdq1_reg       		  0x484		, 25		, 25		
 #define	 reg_a_h_abutnrcompdq0_reg       		  0x484		, 24		, 24		
 #define	 reg_a_h_abutprcompdq4_reg       		  0x484		, 20		, 20		
 #define	 reg_a_h_abutprcompdq3_reg       		  0x484		, 19		, 19		
 #define	 reg_a_h_abutprcompdq2_reg       		  0x484		, 18		, 18		
 #define	 reg_a_h_abutprcompdq1_reg       		  0x484		, 17		, 17		
 #define	 reg_a_h_abutprcompdq0_reg       		  0x484		, 16		, 16		
 #define	 reg_a_h_abutodtpddq4_reg        		  0x484		, 12		, 12		
 #define	 reg_a_h_abutodtpddq3_reg        		  0x484		, 11		, 11		
 #define	 reg_a_h_abutodtpddq2_reg        		  0x484		, 10		, 10		
 #define	 reg_a_h_abutodtpddq1_reg        		  0x484		, 9		, 9		
 #define	 reg_a_h_abutodtpddq0_reg        		  0x484		, 8		, 8		
 #define	 reg_a_h_abutodtpudq4_reg        		  0x484		, 4		, 4		
 #define	 reg_a_h_abutodtpudq3_reg        		  0x484		, 3		, 3		
 #define	 reg_a_h_abutodtpudq2_reg        		  0x484		, 2		, 2		
 #define	 reg_a_h_abutodtpudq1_reg        		  0x484		, 1		, 1		
 #define	 reg_a_h_abutodtpudq0_reg        		  0x484		, 0		, 0		
 #define	 reg_a_h_rxmen0_delay_bp         		  0x4a0		, 26		, 24		
 #define	 reg_a_h_rxmen0_ophsel_bp        		  0x4a0		, 23		, 21		
 #define	 reg_a_h_rxmen0_sdlltap_bp       		  0x4a0		, 20		, 15		
 #define	 reg_a_h_rxmen1_delay_bp         		  0x4a0		, 11		, 9		
 #define	 reg_a_h_rxmen1_ophsel_bp        		  0x4a0		, 8		, 6		
 #define	 reg_a_h_rxmen1_sdlltap_bp       		  0x4a0		, 5		, 0		
 #define	 reg_a_h_rdodt0_delay            		  0x4a4		, 26		, 24		
 #define	 reg_a_h_rdodt0_ophsel           		  0x4a4		, 23		, 21		
 #define	 reg_a_h_rdodt0_dllsel           		  0x4a4		, 20		, 16		
 #define	 reg_a_h_rdodt1_delay            		  0x4a4		, 10		, 8		
 #define	 reg_a_h_rdodt1_ophsel           		  0x4a4		, 7		, 5		
 #define	 reg_a_h_rdodt1_dllsel           		  0x4a4		, 4		, 0		
 #define	 reg_a_h_dm_obsdataen            		  0x4a8		, 28		, 28		
 #define	 reg_a_h_dqobsmuxsel             		  0x4a8		, 27		, 24		
 #define	 reg_a_h_dqout_mux               		  0x4a8		, 23		, 23		
 #define	 reg_a_h_dmout_mux               		  0x4a8		, 22		, 22		
 #define	 reg_a_h_dq_ph90en_bp            		  0x4a8		, 21		, 21		
 #define	 reg_a_h_dqs_ph90en_bp           		  0x4a8		, 20		, 20		
 #define	 reg_a_h_rcvdqsmodsel            		  0x4a8		, 19		, 19		
 #define	 reg_a_h_selfclren               		  0x4a8		, 18		, 18		
 #define	 reg_a_h_wrptrclrb               		  0x4a8		, 17		, 17		
 #define	 reg_a_h_rxm_odiffampen          		  0x4a8		, 16		, 16		
 #define	 reg_a_h_abutobsmodeen           		  0x4a8		, 15		, 15		
 #define	 reg_a_h_odtenb4p5en             		  0x4a8		, 14		, 14		
 #define	 reg_a_h_rxm4p5en                		  0x4a8		, 13		, 13		
 #define	 reg_a_h_tsm_iobufact_bp         		  0x4a8		, 12		, 12		
 #define	 reg_a_h_rxpst_bp                		  0x4a8		, 11		, 11		
 #define	 reg_a_h_odtenb4p5en_r2          		  0x4a8		, 10		, 10		
 #define	 reg_a_h_rxm4p5en_r2             		  0x4a8		, 9		, 9		
 #define	 reg_a_h_wrankphsel              		  0x4a8		, 8		, 6		
 #define	 reg_a_h_rrankdly_4x_cs0         		  0x4a8		, 5		, 3		
 #define	 reg_a_h_rrankdly_4x_cs1         		  0x4a8		, 2		, 0		
 #define	 reg_a_h_rrank_dlldly_cs0        		  0x4ac		, 11		, 6		
 #define	 reg_a_h_rrank_dlldly_cs1        		  0x4ac		, 5		, 0		
 #define	 reg_a_h_cs0_dm_invdelaysel      		  0x4d0		, 5		, 0		
 #define	 reg_a_h_cs0_dq0_invdelaysel     		  0x4d4		, 29		, 24		
 #define	 reg_a_h_cs0_dq1_invdelaysel     		  0x4d4		, 21		, 16		
 #define	 reg_a_h_cs0_dq2_invdelaysel     		  0x4d4		, 13		, 8		
 #define	 reg_a_h_cs0_dq3_invdelaysel     		  0x4d4		, 5		, 0		
 #define	 reg_a_h_cs0_dq4_invdelaysel     		  0x4d8		, 29		, 24		
 #define	 reg_a_h_cs0_dq5_invdelaysel     		  0x4d8		, 21		, 16		
 #define	 reg_a_h_cs0_dq6_invdelaysel     		  0x4d8		, 13		, 8		
 #define	 reg_a_h_cs0_dq7_invdelaysel     		  0x4d8		, 5		, 0		
 #define	 reg_a_h_cs0_dqs_invdelaysel     		  0x4dc		, 29		, 24		
 #define	 reg_a_h_cs0_dqsb_invdelaysel    		  0x4dc		, 13		, 8		
 #define	 reg_a_h_cs0_loop_invdelaysel    		  0x4e0		, 28		, 24		
 #define	 reg_a_h_cs0_dm_invdelayselrx    		  0x4e0		, 13		, 8		
 #define	 reg_a_h_cs0_dq0_invdelayselrx   		  0x4e4		, 29		, 24		
 #define	 reg_a_h_cs0_dq1_invdelayselrx   		  0x4e4		, 21		, 16		
 #define	 reg_a_h_cs0_dq2_invdelayselrx   		  0x4e4		, 13		, 8		
 #define	 reg_a_h_cs0_dq3_invdelayselrx   		  0x4e4		, 5		, 0		
 #define	 reg_a_h_cs0_dq4_invdelayselrx   		  0x4e8		, 29		, 24		
 #define	 reg_a_h_cs0_dq5_invdelayselrx   		  0x4e8		, 21		, 16		
 #define	 reg_a_h_cs0_dq6_invdelayselrx   		  0x4e8		, 13		, 8		
 #define	 reg_a_h_cs0_dq7_invdelayselrx   		  0x4e8		, 5		, 0		
 #define	 reg_a_h_cs0_dqs_invdelayselrx   		  0x4ec		, 29		, 24		
 #define	 reg_a_h_cs0_dqsb_invdelayselrx  		  0x4ec		, 13		, 8		
 #define	 reg_a_h_cs1_dm_invdelaysel      		  0x4f0		, 5		, 0		
 #define	 reg_a_h_cs1_dq0_invdelaysel     		  0x4f4		, 29		, 24		
 #define	 reg_a_h_cs1_dq1_invdelaysel     		  0x4f4		, 21		, 16		
 #define	 reg_a_h_cs1_dq2_invdelaysel     		  0x4f4		, 13		, 8		
 #define	 reg_a_h_cs1_dq3_invdelaysel     		  0x4f4		, 5		, 0		
 #define	 reg_a_h_cs1_dq4_invdelaysel     		  0x4f8		, 29		, 24		
 #define	 reg_a_h_cs1_dq5_invdelaysel     		  0x4f8		, 21		, 16		
 #define	 reg_a_h_cs1_dq6_invdelaysel     		  0x4f8		, 13		, 8		
 #define	 reg_a_h_cs1_dq7_invdelaysel     		  0x4f8		, 5		, 0		
 #define	 reg_a_h_cs1_dqs_invdelaysel     		  0x4fc		, 29		, 24		
 #define	 reg_a_h_cs1_dqsb_invdelaysel    		  0x4fc		, 13		, 8		
 #define	 reg_a_h_cs1_loop_invdelaysel    		  0x500		, 28		, 24		
 #define	 reg_a_h_cs1_dm_invdelayselrx    		  0x500		, 13		, 8		
 #define	 reg_a_h_cs1_dq0_invdelayselrx   		  0x504		, 29		, 24		
 #define	 reg_a_h_cs1_dq1_invdelayselrx   		  0x504		, 21		, 16		
 #define	 reg_a_h_cs1_dq2_invdelayselrx   		  0x504		, 13		, 8		
 #define	 reg_a_h_cs1_dq3_invdelayselrx   		  0x504		, 5		, 0		
 #define	 reg_a_h_cs1_dq4_invdelayselrx   		  0x508		, 29		, 24		
 #define	 reg_a_h_cs1_dq5_invdelayselrx   		  0x508		, 21		, 16		
 #define	 reg_a_h_cs1_dq6_invdelayselrx   		  0x508		, 13		, 8		
 #define	 reg_a_h_cs1_dq7_invdelayselrx   		  0x508		, 5		, 0		
 #define	 reg_a_h_cs1_dqs_invdelayselrx   		  0x50c		, 29		, 24		
 #define	 reg_a_h_cs1_dqsb_invdelayselrx  		  0x50c		, 13		, 8		
 #define	 reg_a_h_rd_train_dqs_default    		  0x520		, 29		, 24		
 #define	 reg_a_h_train_dqs_default       		  0x520		, 21		, 16		
 #define	 reg_a_h_rd_train_dqs_range_max  		  0x520		, 13		, 8		
 #define	 reg_a_h_rd_train_dqs_range_min  		  0x520		, 5		, 0		
 #define	 reg_a_h_rdtrain_check_wrap0     		  0x524		, 15		, 8		
 #define	 reg_a_h_rdtrain_check_wrap1     		  0x524		, 7		, 0		


// RO REGISTER LIST
 #define	 reg_a_h_dqs_idqshigh            		  0x560		, 30		, 30		
 #define	 reg_a_h_tdqs_invdelaysel0       		  0x560		, 21		, 16		
 #define	 reg_a_h_tdqs_invdelaysel1       		  0x560		, 5		, 0		
 #define	 reg_a_h_cycsel                  		  0x564		, 11		, 9		
 #define	 reg_a_h_ophsel                  		  0x564		, 8		, 6		
 #define	 reg_a_h_dllsel                  		  0x564		, 5		, 0		
 #define	 reg_a_h_calib_result_cs0        		  0x568		, 27		, 16		
 #define	 reg_a_h_calib_result_cs1        		  0x568		, 11		, 0		
 #define	 reg_a_h_cs0_value_dqx_invdelaysel		  0x56c		, 13		, 8		
 #define	 reg_a_h_cs1_value_dqx_invdelaysel		  0x570		, 13		, 8		
 #define	 reg_a_h_train_min_for_rd_dq0    		  0x574		, 29		, 24		
 #define	 reg_a_h_train_min_for_rd_dq1    		  0x574		, 21		, 16		
 #define	 reg_a_h_train_min_for_rd_dq2    		  0x574		, 13		, 8		
 #define	 reg_a_h_train_min_for_rd_dq3    		  0x574		, 5		, 0		
 #define	 reg_a_h_train_min_for_rd_dq4    		  0x578		, 29		, 24		
 #define	 reg_a_h_train_min_for_rd_dq5    		  0x578		, 21		, 16		
 #define	 reg_a_h_train_min_for_rd_dq6    		  0x578		, 13		, 8		
 #define	 reg_a_h_train_min_for_rd_dq7    		  0x578		, 5		, 0		
 #define	 reg_a_h_train_min_for_rd_dqs    		  0x57c		, 5		, 0		
 #define	 reg_a_h_train_max_for_rd_dq0    		  0x580		, 29		, 24		
 #define	 reg_a_h_train_max_for_rd_dq1    		  0x580		, 21		, 16		
 #define	 reg_a_h_train_max_for_rd_dq2    		  0x580		, 13		, 8		
 #define	 reg_a_h_train_max_for_rd_dq3    		  0x580		, 5		, 0		
 #define	 reg_a_h_train_max_for_rd_dq4    		  0x584		, 29		, 24		
 #define	 reg_a_h_train_max_for_rd_dq5    		  0x584		, 21		, 16		
 #define	 reg_a_h_train_max_for_rd_dq6    		  0x584		, 13		, 8		
 #define	 reg_a_h_train_max_for_rd_dq7    		  0x584		, 5		, 0		
 #define	 reg_a_h_train_max_for_rd_dqs    		  0x588		, 5		, 0		
 #define	 reg_a_h_train_result_for_rd_base_dqs		  0x58c		, 23		, 18		
 #define	 reg_a_h_change_rd_dqs_default   		  0x58c		, 5		, 5		
 #define	 reg_a_h_left_boundary_overflow_for_rd		  0x58c		, 3		, 3		
 #define	 reg_a_h_right_boundary_overflow_for_rd		  0x58c		, 2		, 2		
 #define	 reg_a_h_rd_train_readback_data_dq0		  0x590		, 31		, 16		
 #define	 reg_a_h_rd_train_readback_data_dq1		  0x590		, 15		, 0		
 #define	 reg_a_h_rd_train_readback_data_dq2		  0x594		, 31		, 16		
 #define	 reg_a_h_rd_train_readback_data_dq3		  0x594		, 15		, 0		
 #define	 reg_a_h_rd_train_readback_data_dq4		  0x598		, 31		, 16		
 #define	 reg_a_h_rd_train_readback_data_dq5		  0x598		, 15		, 0		
 #define	 reg_a_h_rd_train_readback_data_dq6		  0x59c		, 31		, 16		
 #define	 reg_a_h_rd_train_readback_data_dq7		  0x59c		, 15		, 0		
 #define	 reg_a_h_change_dqs_default      		  0x5a0		, 16		, 16		
 #define	 reg_a_h_train_min_for_dqs       		  0x5a0		, 5		, 0		
 #define	 reg_a_h_train_min_for_dq0       		  0x5a4		, 29		, 24		
 #define	 reg_a_h_train_min_for_dq1       		  0x5a4		, 21		, 16		
 #define	 reg_a_h_train_min_for_dq2       		  0x5a4		, 13		, 8		
 #define	 reg_a_h_train_min_for_dq3       		  0x5a4		, 5		, 0		
 #define	 reg_a_h_train_min_for_dq4       		  0x5a8		, 29		, 24		
 #define	 reg_a_h_train_min_for_dq5       		  0x5a8		, 21		, 16		
 #define	 reg_a_h_train_min_for_dq6       		  0x5a8		, 13		, 8		
 #define	 reg_a_h_train_min_for_dq7       		  0x5a8		, 5		, 0		
 #define	 reg_a_h_train_max_for_dqs       		  0x5ac		, 5		, 0		
 #define	 reg_a_h_train_max_for_dq0       		  0x5b0		, 29		, 24		
 #define	 reg_a_h_train_max_for_dq1       		  0x5b0		, 21		, 16		
 #define	 reg_a_h_train_max_for_dq2       		  0x5b0		, 13		, 8		
 #define	 reg_a_h_train_max_for_dq3       		  0x5b0		, 5		, 0		
 #define	 reg_a_h_train_max_for_dq4       		  0x5b4		, 29		, 24		
 #define	 reg_a_h_train_max_for_dq5       		  0x5b4		, 21		, 16		
 #define	 reg_a_h_train_max_for_dq6       		  0x5b4		, 13		, 8		
 #define	 reg_a_h_train_max_for_dq7       		  0x5b4		, 5		, 0		
 #define	 reg_a_h_rdtrain_vref_max        		  0x5b8		, 15		, 8		
 #define	 reg_a_h_rdtrain_vref_min        		  0x5b8		, 7		, 0		


 #define	 reg_bit_sel                     		  0x0e8		, 17		, 14		
 #define	 reg_bist_data_obs_sel           		  0x0e8		, 13		, 13		
 #define	 reg_bist_addr_pattern_sel       		  0x0e8		, 12		, 10		
 #define	 reg_bist_data_pattern_sel       		  0x0e8		, 9		, 7		
 #define	 reg_bist_mode_sel               		  0x0e8		, 6		, 4		
 #define	 reg_bist_serial_wr_stop         		  0x0e8		, 3		, 3		
 #define	 reg_bist_soft_rstn              		  0x0e8		, 2		, 2		
 #define	 reg_bist_start                  		  0x0e8		, 1		, 1		
 #define	 reg_bist_en                     		  0x0e8		, 0		, 0		
 #define	 reg_bist_start_addr             		  0x0ec		, 31		, 0		
 #define	 reg_bist_end_addr               		  0x0f0		, 31		, 0		
 #define	 reg_bist_data                   		  0x0f4		, 31		, 0		
 #define	 reg_bist_data0                  		  0x0f8		, 31		, 0		
 #define	 reg_bist_data1                  		  0x0fc		, 31		, 0		
 #define	 reg_bist_data2                  		  0x100		, 31		, 0		
 #define	 reg_bist_data3                  		  0x104		, 31		, 0		
 #define	 reg_bist_prbs_sel               		  0x108		, 0		, 0		
 #define	 reg_bist_data_mask_0            		  0x10c		, 31		, 0		
 #define	 reg_bist_data_mask_1            		  0x110		, 31		, 0		
 #define	 reg_bist_data_mask_2            		  0x114		, 15		, 0		
 #define	 reg_bist_ecnt_set               		  0x118		, 7		, 0		
 #define	 reg_bist_eaddr_set              		  0x11c		, 31		, 0		
 #define	 reg_bist_ebit_set_0             		  0x120		, 31		, 0		
 #define	 reg_bist_ebit_set_1             		  0x124		, 31		, 0		
 #define	 reg_bist_ebit_set_2             		  0x128		, 31		, 0		
 #define	 reg_bist_done 0x2c8,0,0
 #define	 reg_bist_pass 0x2c8,1,1 
 #define	 reg_bist_error_addr_obs_31_0 0x2c,31,0
 #define	 reg_bist_act_data_obs_sel_0_31_0 0x310,31,0
 #define   reg_bist_act_data_obs_sel_1_31_0 0x30c,31,0
 #define   reg_bist_act_data_obs_sel_2_31_0 0x308,31,0
 #define   reg_bist_act_data_obs_sel_3_31_0 0x304,31,0
 #define   reg_bist_exp_data_obs_sel_0_31_0 0x320,31,0
 #define   reg_bist_exp_data_obs_sel_1_31_0 0x31c,31,0
 #define   reg_bist_exp_data_obs_sel_2_31_0 0x318,31,0
 #define   reg_bist_exp_data_obs_sel_3_31_0 0x314,31,0



//void tr_test();
void bist_op(uint32_t bist_mode, uint32_t bist_start_addr, uint32_t bist_end_addr);
//void phy_analog_config();


#endif

