//---------------------------------------------------------------------------
// Across
//---------------------------------------------------------------------------

/////////////////////////////////////////////////////////////////////////////

//-- I2C0
#define	REG_I2C0_CON			(REG_I2C0_BASE + 0x00)
#define	REG_I2C0_TAR			(REG_I2C0_BASE + 0x04)
#define	REG_I2C0_SAR			(REG_I2C0_BASE + 0x08)
#define	REG_I2C0_HS_MADDR		(REG_I2C0_BASE + 0x0c)
#define	REG_I2C0_DATA_CMD		(REG_I2C0_BASE + 0x10)
#define	REG_I2C0_SS_SCL_HCNT		(REG_I2C0_BASE + 0x14)
#define	REG_I2C0_SS_SCL_LCNT		(REG_I2C0_BASE + 0x18)
#define	REG_I2C0_FS_SCL_HCNT		(REG_I2C0_BASE + 0x1c)
#define	REG_I2C0_FS_SCL_LCNT		(REG_I2C0_BASE + 0x20)
#define	REG_I2C0_HS_SCL_HCNT		(REG_I2C0_BASE + 0x24)
#define	REG_I2C0_HS_SCL_LCNT		(REG_I2C0_BASE + 0x28)
#define	REG_I2C0_INTR_STAT		(REG_I2C0_BASE + 0x2c)
#define	REG_I2C0_INTR_MASK		(REG_I2C0_BASE + 0x30)
#define	REG_I2C0_RAW_INTR_STAT		(REG_I2C0_BASE + 0x34)
#define	REG_I2C0_RX_TL			(REG_I2C0_BASE + 0x38)
#define	REG_I2C0_TX_TL			(REG_I2C0_BASE + 0x3c)
#define	REG_I2C0_CLR_INTR		(REG_I2C0_BASE + 0x40)
#define	REG_I2C0_CLR_RX_UNDER		(REG_I2C0_BASE + 0x44)
#define	REG_I2C0_CLR_RX_OVER		(REG_I2C0_BASE + 0x48)
#define	REG_I2C0_CLR_TX_OVER		(REG_I2C0_BASE + 0x4c)
#define	REG_I2C0_CLR_RD_REQ		(REG_I2C0_BASE + 0x50)
#define	REG_I2C0_CLR_TX_ABRT		(REG_I2C0_BASE + 0x54)
#define	REG_I2C0_CLR_RX_DONE		(REG_I2C0_BASE + 0x58)
#define	REG_I2C0_CLR_ACTIVITY		(REG_I2C0_BASE + 0x5c)
#define	REG_I2C0_CLR_STOP_DET		(REG_I2C0_BASE + 0x60)
#define	REG_I2C0_CLR_START_DET		(REG_I2C0_BASE + 0x64)
#define	REG_I2C0_CLR_GEN_CALL		(REG_I2C0_BASE + 0x68)
#define	REG_I2C0_ENABLE			(REG_I2C0_BASE + 0x6c)
#define	REG_I2C0_STATUS			(REG_I2C0_BASE + 0x70)
#define	REG_I2C0_TXFLR			(REG_I2C0_BASE + 0x74)
#define	REG_I2C0_RXFLR			(REG_I2C0_BASE + 0x78)
#define	REG_I2C0_SDA_HOLD		(REG_I2C0_BASE + 0x7c)
#define	REG_I2C0_TX_ABRT_SOURCE		(REG_I2C0_BASE + 0x80)
#define	REG_I2C0_SLV_DATA_NACK_ONLY	(REG_I2C0_BASE + 0x84)
#define	REG_I2C0_DMA_CR			(REG_I2C0_BASE + 0x88)
#define	REG_I2C0_DMA_TDLR		(REG_I2C0_BASE + 0x8c)
#define	REG_I2C0_DMA_RDLR		(REG_I2C0_BASE + 0x90)
#define	REG_I2C0_SDA_SETUP		(REG_I2C0_BASE + 0x94)
#define	REG_I2C0_ACK_GENERAL_CALL	(REG_I2C0_BASE + 0x98)
#define	REG_I2C0_ENABLE_STATUS		(REG_I2C0_BASE + 0x9c)
#define	REG_I2C0_FS_SPKLEN		(REG_I2C0_BASE + 0xa0)
#define	REG_I2C0_HS_SPKLEN		(REG_I2C0_BASE + 0xa4)
#define	REG_I2C0_COMP_PARAM_1		(REG_I2C0_BASE + 0xf4)
#define	REG_I2C0_COMP_VERSION		(REG_I2C0_BASE + 0xf8)
#define	REG_I2C0_COMP_TYPE		(REG_I2C0_BASE + 0xfc)

//-- I2C1
#define	REG_I2C1_CON			(REG_I2C1_BASE + 0x00)
#define	REG_I2C1_TAR			(REG_I2C1_BASE + 0x04)
#define	REG_I2C1_SAR			(REG_I2C1_BASE + 0x08)
#define	REG_I2C1_HS_MADDR		(REG_I2C1_BASE + 0x0c)
#define	REG_I2C1_DATA_CMD		(REG_I2C1_BASE + 0x10)
#define	REG_I2C1_SS_SCL_HCNT		(REG_I2C1_BASE + 0x14)
#define	REG_I2C1_SS_SCL_LCNT		(REG_I2C1_BASE + 0x18)
#define	REG_I2C1_FS_SCL_HCNT		(REG_I2C1_BASE + 0x1c)
#define	REG_I2C1_FS_SCL_LCNT		(REG_I2C1_BASE + 0x20)
#define	REG_I2C1_HS_SCL_HCNT		(REG_I2C1_BASE + 0x24)
#define	REG_I2C1_HS_SCL_LCNT		(REG_I2C1_BASE + 0x28)
#define	REG_I2C1_INTR_STAT		(REG_I2C1_BASE + 0x2c)
#define	REG_I2C1_INTR_MASK		(REG_I2C1_BASE + 0x30)
#define	REG_I2C1_RAW_INTR_STAT		(REG_I2C1_BASE + 0x34)
#define	REG_I2C1_RX_TL			(REG_I2C1_BASE + 0x38)
#define	REG_I2C1_TX_TL			(REG_I2C1_BASE + 0x3c)
#define	REG_I2C1_CLR_INTR		(REG_I2C1_BASE + 0x40)
#define	REG_I2C1_CLR_RX_UNDER		(REG_I2C1_BASE + 0x44)
#define	REG_I2C1_CLR_RX_OVER		(REG_I2C1_BASE + 0x48)
#define	REG_I2C1_CLR_TX_OVER		(REG_I2C1_BASE + 0x4c)
#define	REG_I2C1_CLR_RD_REQ		(REG_I2C1_BASE + 0x50)
#define	REG_I2C1_CLR_TX_ABRT		(REG_I2C1_BASE + 0x54)
#define	REG_I2C1_CLR_RX_DONE		(REG_I2C1_BASE + 0x58)
#define	REG_I2C1_CLR_ACTIVITY		(REG_I2C1_BASE + 0x5c)
#define	REG_I2C1_CLR_STOP_DET		(REG_I2C1_BASE + 0x60)
#define	REG_I2C1_CLR_START_DET		(REG_I2C1_BASE + 0x64)
#define	REG_I2C1_CLR_GEN_CALL		(REG_I2C1_BASE + 0x68)
#define	REG_I2C1_ENABLE			(REG_I2C1_BASE + 0x6c)
#define	REG_I2C1_STATUS			(REG_I2C1_BASE + 0x70)
#define	REG_I2C1_TXFLR			(REG_I2C1_BASE + 0x74)
#define	REG_I2C1_RXFLR			(REG_I2C1_BASE + 0x78)
#define	REG_I2C1_SDA_HOLD		(REG_I2C1_BASE + 0x7c)
#define	REG_I2C1_TX_ABRT_SOURCE		(REG_I2C1_BASE + 0x80)
#define	REG_I2C1_SLV_DATA_NACK_ONLY	(REG_I2C1_BASE + 0x84)
#define	REG_I2C1_DMA_CR			(REG_I2C1_BASE + 0x88)
#define	REG_I2C1_DMA_TDLR		(REG_I2C1_BASE + 0x8c)
#define	REG_I2C1_DMA_RDLR		(REG_I2C1_BASE + 0x90)
#define	REG_I2C1_SDA_SETUP		(REG_I2C1_BASE + 0x94)
#define	REG_I2C1_ACK_GENERAL_CALL	(REG_I2C1_BASE + 0x98)
#define	REG_I2C1_ENABLE_STATUS		(REG_I2C1_BASE + 0x9c)
#define	REG_I2C1_FS_SPKLEN		(REG_I2C1_BASE + 0xa0)
#define	REG_I2C1_HS_SPKLEN		(REG_I2C1_BASE + 0xa4)
#define	REG_I2C1_COMP_PARAM_1		(REG_I2C1_BASE + 0xf4)
#define	REG_I2C1_COMP_VERSION		(REG_I2C1_BASE + 0xf8)
#define	REG_I2C1_COMP_TYPE		(REG_I2C1_BASE + 0xfc)

//-- I2C Index
#define REG_I2C_BASE(i)	((i==0) ? REG_I2C0_BASE : REG_I2C1_BASE)

#define	REG_I2C_CON(i)			(REG_I2C_BASE(i) + 0x00)
#define	REG_I2C_TAR(i)			(REG_I2C_BASE(i) + 0x04)
#define	REG_I2C_SAR(i)			(REG_I2C_BASE(i) + 0x08)
#define	REG_I2C_HS_MADDR(i)		(REG_I2C_BASE(i) + 0x0c)
#define	REG_I2C_DATA_CMD(i)		(REG_I2C_BASE(i) + 0x10)
#define	REG_I2C_SS_SCL_HCNT(i)		(REG_I2C_BASE(i) + 0x14)
#define	REG_I2C_SS_SCL_LCNT(i)		(REG_I2C_BASE(i) + 0x18)
#define	REG_I2C_FS_SCL_HCNT(i)		(REG_I2C_BASE(i) + 0x1c)
#define	REG_I2C_FS_SCL_LCNT(i)		(REG_I2C_BASE(i) + 0x20)
#define	REG_I2C_HS_SCL_HCNT(i)		(REG_I2C_BASE(i) + 0x24)
#define	REG_I2C_HS_SCL_LCNT(i)		(REG_I2C_BASE(i) + 0x28)
#define	REG_I2C_INTR_STAT(i)		(REG_I2C_BASE(i) + 0x2c)
#define	REG_I2C_INTR_MASK(i)		(REG_I2C_BASE(i) + 0x30)
#define	REG_I2C_RAW_INTR_STAT(i)	(REG_I2C_BASE(i) + 0x34)
#define	REG_I2C_RX_TL(i)		(REG_I2C_BASE(i) + 0x38)
#define	REG_I2C_TX_TL(i)		(REG_I2C_BASE(i) + 0x3c)
#define	REG_I2C_CLR_INTR(i)		(REG_I2C_BASE(i) + 0x40)
#define	REG_I2C_CLR_RX_UNDER(i)		(REG_I2C_BASE(i) + 0x44)
#define	REG_I2C_CLR_RX_OVER(i)		(REG_I2C_BASE(i) + 0x48)
#define	REG_I2C_CLR_TX_OVER(i)		(REG_I2C_BASE(i) + 0x4c)
#define	REG_I2C_CLR_RD_REQ(i)		(REG_I2C_BASE(i) + 0x50)
#define	REG_I2C_CLR_TX_ABRT(i)		(REG_I2C_BASE(i) + 0x54)
#define	REG_I2C_CLR_RX_DONE(i)		(REG_I2C_BASE(i) + 0x58)
#define	REG_I2C_CLR_ACTIVITY(i)		(REG_I2C_BASE(i) + 0x5c)
#define	REG_I2C_CLR_STOP_DET(i)		(REG_I2C_BASE(i) + 0x60)
#define	REG_I2C_CLR_START_DET(i)	(REG_I2C_BASE(i) + 0x64)
#define	REG_I2C_CLR_GEN_CALL(i)		(REG_I2C_BASE(i) + 0x68)
#define	REG_I2C_ENABLE(i)		(REG_I2C_BASE(i) + 0x6c)
#define	REG_I2C_STATUS(i)		(REG_I2C_BASE(i) + 0x70)
#define	REG_I2C_TXFLR(i)		(REG_I2C_BASE(i) + 0x74)
#define	REG_I2C_RXFLR(i)		(REG_I2C_BASE(i) + 0x78)
#define	REG_I2C_SDA_HOLD(i)		(REG_I2C_BASE(i) + 0x7c)
#define	REG_I2C_TX_ABRT_SOURCE(i)	(REG_I2C_BASE(i) + 0x80)
#define	REG_I2C_SLV_DATA_NACK_ONLY(i)	(REG_I2C_BASE(i) + 0x84)
#define	REG_I2C_DMA_CR(i)		(REG_I2C_BASE(i) + 0x88)
#define	REG_I2C_DMA_TDLR(i)		(REG_I2C_BASE(i) + 0x8c)
#define	REG_I2C_DMA_RDLR(i)		(REG_I2C_BASE(i) + 0x90)
#define	REG_I2C_SDA_SETUP(i)		(REG_I2C_BASE(i) + 0x94)
#define	REG_I2C_ACK_GENERAL_CALL(i)	(REG_I2C_BASE(i) + 0x98)
#define	REG_I2C_ENABLE_STATUS(i)	(REG_I2C_BASE(i) + 0x9c)
#define	REG_I2C_FS_SPKLEN(i)		(REG_I2C_BASE(i) + 0xa0)
#define	REG_I2C_HS_SPKLEN(i)		(REG_I2C_BASE(i) + 0xa4)
#define	REG_I2C_COMP_PARAM_1(i)		(REG_I2C_BASE(i) + 0xf4)
#define	REG_I2C_COMP_VERSION(i)		(REG_I2C_BASE(i) + 0xf8)
#define	REG_I2C_COMP_TYPE(i)		(REG_I2C_BASE(i) + 0xfc)

/////////////////////////////////////////////////////////////////////////////
// EOF

