#ifndef _DRAM_MAP_H_
#define _DRAM_MAP_H_


/////////////////////////////////////////////////////////////////////////////
// TEST_SCENARIO:Encode in Camera Mode
/////////////////////////////////////////////////////////////////////////////
#ifdef USE_AXBRIDGE
// AXBridge対応版 ARM(Linux)用 マッピング 6バンク版対応
#define	DRAM_OFST_CPU_PROG			 (ADR_MEM_BASE + 0x00000000)
#define	DRAM_OFST_IMG_SPU_0			 (ADR_MEM_BASE + 0x32000000)		//(0x04000000)
#define	DRAM_OFST_IMG_SPU_1			 (ADR_MEM_BASE + 0x323F6000)		//(0x04400000)
#define	DRAM_OFST_IMG_MIX_0			 (ADR_MEM_BASE + 0x327EC000)		//(0x04800000)
#define	DRAM_OFST_IMG_MIX_1			 (ADR_MEM_BASE + 0x32BE2000)		//(0x04c00000)
//#define	DRAM_OFST_IMG_DEF			 (ADR_MEM_BASE + 0x32FD8000)		//(0x05000000)
//#define	DRAM_OFST_IMG_3A0_0			 (0x05000400)
//#define	DRAM_OFST_IMG_3A0_1			 (0x05009a00)
//#define	DRAM_OFST_IMG_3A1_0			 (0x05013000)
//#define	DRAM_OFST_IMG_3A1_1			 (0x0501c600)
//#define	DRAM_OFST_ISP_3A_0			 (0x05025c00)
//#define	DRAM_OFST_ISP_3A_1			 (0x0502f200)
#define	DRAM_OFST_ISP_SHAD			 (ADR_MEM_BASE + 0x32FDA000)		//(0x05038800)
#define	DRAM_OFST_ISP_NR_0			 (ADR_MEM_BASE + 0x32FDC000)		//(0x05100000)
#define	DRAM_OFST_ISP_NR_1			 (ADR_MEM_BASE + 0x333D2000)		//(0x05550000)

#define	DRAM_OFST_ISP_SCL0_0		 (ADR_MEM_BASE + 0x337C8000)		//(0x05900000)
#define	DRAM_OFST_ISP_SCL0_1		 (ADR_MEM_BASE + 0x33BBE000)		//(0x05D00000)
#define	DRAM_OFST_ISP_SCL0_2		 (ADR_MEM_BASE + 0x33FB4000)
#define	DRAM_OFST_ISP_SCL0_3		 (ADR_MEM_BASE + 0x343AA000)
#define	DRAM_OFST_ISP_SCL0_4		 (ADR_MEM_BASE + 0x347A0000)
#define	DRAM_OFST_ISP_SCL0_5		 (ADR_MEM_BASE + 0x34B96000)
#define	DRAM_OFST_ISP_SCL1_0		 (ADR_MEM_BASE + 0x34F8C000)		//(0x06100000)
#define	DRAM_OFST_ISP_SCL1_1		 (ADR_MEM_BASE + 0x35022000)		//(0x06196000)
#define	DRAM_OFST_ISP_SCL1_2		 (ADR_MEM_BASE + 0x350B8000)
#define	DRAM_OFST_ISP_SCL1_3		 (ADR_MEM_BASE + 0x3514E000)
#define	DRAM_OFST_ISP_SCL1_4		 (ADR_MEM_BASE + 0x351E4000)
#define	DRAM_OFST_ISP_SCL1_5		 (ADR_MEM_BASE + 0x3527A000)
#define	DRAM_OFST_ISP_SCL2_0		 (ADR_MEM_BASE + 0x35310000)		//(0x0622c000)
#define	DRAM_OFST_ISP_SCL2_1		 (ADR_MEM_BASE + 0x35342000)		//(0x06252000)
#define	DRAM_OFST_ISP_SCL2_2		 (ADR_MEM_BASE + 0x35374000)
#define	DRAM_OFST_ISP_SCL2_3		 (ADR_MEM_BASE + 0x353A6000)
#define	DRAM_OFST_ISP_SCL2_4		 (ADR_MEM_BASE + 0x353D8000)
#define	DRAM_OFST_ISP_SCL2_5		 (ADR_MEM_BASE + 0x3540A000)
#define	DRAM_OFST_ISP_SCL3_0		 (ADR_MEM_BASE + 0x3543C000)		//(0x06278000)
#define	DRAM_OFST_ISP_SCL3_1		 (ADR_MEM_BASE + 0x35832000)		//(0x064d0000)
#define	DRAM_OFST_ISP_SCL3_2		 (ADR_MEM_BASE + 0x35C28000)
#define	DRAM_OFST_ISP_SCL3_3		 (ADR_MEM_BASE + 0x3601E000)
#define	DRAM_OFST_ISP_SCL3_4		 (ADR_MEM_BASE + 0x36414000)
#define	DRAM_OFST_ISP_SCL3_5		 (ADR_MEM_BASE + 0x3680A000)

#else
// 画像出力確認デバッグ版ARM(non OS)用 マッピング
#define	DRAM_OFST_CPU_PROG		 (ADR_MEM_BASE + 0x00000000)
#define	DRAM_OFST_IMG_SPU_0			 (ADR_MEM_BASE + 0x32000000)		//(0x04000000)
#define	DRAM_OFST_IMG_SPU_1			 (ADR_MEM_BASE + 0x323F6000)		//(0x04400000)
#define	DRAM_OFST_IMG_MIX_0			 (ADR_MEM_BASE + 0x327EC000)		//(0x04800000)
#define	DRAM_OFST_IMG_MIX_1			 (ADR_MEM_BASE + 0x32BE2000)		//(0x04c00000)
//#define	DRAM_OFST_IMG_DEF		 (ADR_MEM_BASE + 0x05000000)
//#define	DRAM_OFST_IMG_3A_AWE_0		 (ADR_MEM_BASE + 0x05010000)
//#define	DRAM_OFST_IMG_3A_AWE_1		 (ADR_MEM_BASE + 0x05020000)
//#define	DRAM_OFST_IMG_3A_AE0_0		 (ADR_MEM_BASE + 0x05030000)
//#define	DRAM_OFST_IMG_3A_AE0_1		 (ADR_MEM_BASE + 0x05031000)
//#define	DRAM_OFST_IMG_3A_AE0_0		 (ADR_MEM_BASE + 0x05032000)
//#define	DRAM_OFST_IMG_3A_AE0_1		 (ADR_MEM_BASE + 0x05033000)
#define	DRAM_OFST_ISP_3A_0		 (ADR_MEM_BASE + 0x05040000)
#define	DRAM_OFST_ISP_3A_1		 (ADR_MEM_BASE + 0x05050000)
//#define	DRAM_OFST_ISP_SHAD		 (ADR_MEM_BASE + 0x05100000)
#define	DRAM_OFST_ISP_SHAD		 (ADR_MEM_BASE + 0x32FDA000)
#define	DRAM_OFST_ISP_NR_0		 (ADR_MEM_BASE + 0x05500000)
#define	DRAM_OFST_ISP_NR_1		 (ADR_MEM_BASE + 0x05900000)
#define	DRAM_OFST_ISP_SCL0_0		 (ADR_MEM_BASE + 0x05D00000)
#define	DRAM_OFST_ISP_SCL0_1		 (ADR_MEM_BASE + 0x06100000)
#define	DRAM_OFST_ISP_SCL1_0		 (ADR_MEM_BASE + 0x06500000)
#define	DRAM_OFST_ISP_SCL1_1		 (ADR_MEM_BASE + 0x06900000)
#define	DRAM_OFST_ISP_SCL2_0		 (ADR_MEM_BASE + 0x06D00000)
#define	DRAM_OFST_ISP_SCL2_1		 (ADR_MEM_BASE + 0x07100000)
#define	DRAM_OFST_ISP_SCL3_0		 (ADR_MEM_BASE + 0x07500000)
#define	DRAM_OFST_ISP_SCL3_1		 (ADR_MEM_BASE + 0x07900000)
#endif

//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// EOF

#endif  //  _DRAM_MAP_H_
