

#define D_HMAX                    0x226  //60fps

#define D_NMP                     2      //rx pix_clk: 0,162 1,297 2,324
#define D_NVC1                    0      //video_clk1: 0,297mhz 1,148.5mhz 2,13.5mhz
#define D_NVC2_S1                 0x3F
#define D_NVC2_S2                 0x00   //video_clk2: 0x3f 0,297 0x3f 1,148 0x3f 4,74.25

//UHD60_YUV422_8
#define img_in_h_size             4400
#define img_in_v_size             2250
#define img_in_h_vld_size         3864
#define img_in_v_vld_size         2229 // 1117 instead of 1116, due to CCHG update, 2023-07-11.

//Regs of MIPI-RX
#define D_MODE_P0_OPERATION       0x2
#define D_PHYA_RX_MODE            0x2
#define D_MODE_P0_PIX_PARA        0x1
#define D_DPHY_P0_MODE_LANENUM    0x3 // 4 lane MODE
#define D_DPHY_P0_LP_SYNC_OFF     0x0
#define D_DPHY_P0_MODE_HSDM_OFF   0x0
#define D_DPHY_P0_MODE_MSB_FIRST  0x1 // 1'h0 NG(?)
#define D_DPHY_P0_MODE_LPOP_OFF   0x0

#define D_DPHY_P0_TIME_HS_ON      0
//#define D_DPHY_P0_TIME_RES_ON     0x0020 // for os05a20 742.5 mbps 0x11~0x37 is ok
#define D_DPHY_P0_TIME_RES_ON     0x20 // for imx415 891 mpbs 0x0d~0x26 is ok

#define D_APP_P0_CHK_VENA         0x1
#define D_APP_P0_CHK_HENA         0x1
#define D_APP_P0_CHK_VSIZE        img_in_v_vld_size
#define D_APP_P0_CHK_HSIZE        img_in_h_vld_size
#define D_LINK_P0_RST_N           1
#define D_PHYA_RX_IREF_POW_EN     1
#define D_PHYA_RX_D0_HS_AMP_POW_EN  1
#define D_PHYA_RX_D1_HS_AMP_POW_EN  1
#define D_PHYA_RX_D2_HS_AMP_POW_EN  1
#define D_PHYA_RX_D3_HS_AMP_POW_EN  1
#define D_PHYA_RX_C0_HS_AMP_POW_EN  1
#define D_PHYA_RX_D0_LP_AMP_POW_EN  1
#define D_PHYA_RX_D1_LP_AMP_POW_EN  1
#define D_PHYA_RX_D2_LP_AMP_POW_EN  1
#define D_PHYA_RX_D3_LP_AMP_POW_EN  1
#define D_PHYA_RX_C0_LP_AMP_POW_EN  1

// Regs of MIPI_TX
#define D_DPHY_P0_TX_TIME_T_LPX          20
#define D_DPHY_P0_TX_TIME_T_CLK_PREPARE  10
#define D_DPHY_P0_TX_TIME_T_CLK_ZERO     80
#define D_DPHY_P0_TX_TIME_T_CLK_PRE      0
#define D_DPHY_P0_TX_TIME_T_HS_PREPARE   12
#define D_DPHY_P0_TX_TIME_T_HS_ZERO      30
#define D_DPHY_P0_TX_TIME_T_HS_SOT       0
#define D_DPHY_P0_TX_TIME_T_HS_EOT       15
#define D_DPHY_P0_TX_TIME_T_CLK_POST     0
#define D_DPHY_P0_TX_TIME_T_CLK_EOT      15
#define D_DPHY_P0_TX_TIME_T_WAKEUP       400
#define D_DPHY_P0_TX_LP11  3
#define D_DPHY_P0_TX_LP10  2
#define D_DPHY_P0_TX_LP01  1
#define D_DPHY_P0_TX_LP00  0
#define D_CSI2_P0_TX_TC  0
#define D_CSI2_P0_TX_TS  0
#define D_MODE_LANENUM  3
#define D_PHYA_PLL_PDIV   0 // Input reference clock divider: Divider ratio  (PDIV + 1)
#define D_PHYA_PLL_N1DIV  0 // High Speed Feedback clock divider: Divider ratio: 1/2/4/8
#define D_PHYA_PLL_N2DIV  54 // Feedback clock divider: Divider ratio  (N2DIV + 1)
#define D_PHYA_PLL_K1DIV  0 // Output clock divider for CLK_P/N_O : Divider ratio : 1/2/4/8
#define D_PHYA_PLL_K2DIV  0 // Output clock divider-1 for LS_CLK_O : Divider ratio : 1/2/4/8
#define D_PHYA_PLL_K3DIV  7 // Output clock divider-2 for LS_CLK_O : Divider ratio  (K3DIV + 1)


