1.ES2_FHD60_YUV422_8.mp4
2.ES2_UHD30_YUV422_8.mp4
3.ES2_UHD60_YUV422_8.mp4
4.ES2_FHD60_RGB888.mp4
5.ES2_UHD30_RGB888.mp4
以上五个视频为《L322-ES2-test-report.xlsx》No6 Sheet中的测试视频。

2025/06/16：
ES2_UHD60_YUV422_8_AF_DEFAULT.mp4没设AF，默认读出来的值如下
LISOC_AF->addr_0x04.V_P_AREA_SIZE:      1944.
LISOC_AF->addr_0x04.H_P_AREA_SIZE:      3072.
LISOC_AF->addr_0x08.V_OFFSET:               108.
LISOC_AF->addr_0x08.H_OFFSET:               384.
LISOC_AF->addr_0x0C.V_DIV:                      1.
LISOC_AF->addr_0x0C.H_DIV:                      1.
LISOC_AF->addr_0x10.SSB:                          16.
ES2_UHD60_YUV422_8_AF_INIT.mp4参照仿真初始化了AF，读出来的值如下
LISOC_AF->addr_0x04.V_P_AREA_SIZE:      324.
LISOC_AF->addr_0x04.H_P_AREA_SIZE:      512.
LISOC_AF->addr_0x08.V_OFFSET:                108.
LISOC_AF->addr_0x08.H_OFFSET:                384.
LISOC_AF->addr_0x0C.V_DIV:                       6.
LISOC_AF->addr_0x0C.H_DIV:                       6.
LISOC_AF->addr_0x10.SSB:                           12.

2025/06/18：
ES2_UHD30_RAW12_THRU.mp4
ES2_FHD60_RAW12_THRU.mp4
uhd30/FHD60 THRU的视频
UHD60 THRU NG了。
ES2_UHD60_RAW_THRU_RX_PIX_CLK_324.mp4是设置nmp 324的效果，抖动，但是不丢帧。
ES2_UHD60_RAW_THRU_RX_PIX_CLK_297.mp4是设置nmp 297的效果，抖动，丢帧很严重，CRC错误。

设置如下：
#define D_NMP                     1      //rx pix_clk: 0,162 1,297 2,324
#define D_NVC1                    1      //video_clk1: 0,297mhz 1,148.5mhz 2,13.5mhz
#define D_NVC2_S1                 0x3F
#define D_NVC2_S2                 0x01   //video_clk2: 0x3f 0,297 0x3f 1,148 0x3f 4,74.25

//UHD60_YUV422_8
#define img_in_h_size             4400
#define img_in_v_size             2250

// Regs of MIPI_TX
#define D_DPHY_P0_TX_TIME_T_LPX          20
#define D_DPHY_P0_TX_TIME_T_CLK_PREPARE  10
#define D_DPHY_P0_TX_TIME_T_CLK_ZERO     80
#define D_DPHY_P0_TX_TIME_T_CLK_PRE      0
#define D_DPHY_P0_TX_TIME_T_HS_PREPARE   12
#define D_DPHY_P0_TX_TIME_T_HS_ZERO      30
#define D_DPHY_P0_TX_TIME_T_HS_SOT       0
#define D_DPHY_P0_TX_TIME_T_HS_EOT       15
#define D_DPHY_P0_TX_TIME_T_CLK_POST     0
#define D_DPHY_P0_TX_TIME_T_CLK_EOT      15
#define D_DPHY_P0_TX_TIME_T_WAKEUP       400
#define D_DPHY_P0_TX_LP11  3
#define D_DPHY_P0_TX_LP10  2
#define D_DPHY_P0_TX_LP01  1
#define D_DPHY_P0_TX_LP00  0
#define D_CSI2_P0_TX_TC  0
#define D_CSI2_P0_TX_TS  0
#define D_MODE_LANENUM  3
#define D_PHYA_PLL_PDIV   0 // Input reference clock divider: Divider ratio  (PDIV + 1)
#define D_PHYA_PLL_N1DIV  0 // High Speed Feedback clock divider: Divider ratio: 1/2/4/8
#define D_PHYA_PLL_N2DIV  54 // Feedback clock divider: Divider ratio  (N2DIV + 1)
#define D_PHYA_PLL_K1DIV  0 // Output clock divider for CLK_P/N_O : Divider ratio : 1/2/4/8
#define D_PHYA_PLL_K2DIV  0 // Output clock divider-1 for LS_CLK_O : Divider ratio : 1/2/4/8
#define D_PHYA_PLL_K3DIV  7 // Output clock divider-2 for LS_CLK_O : Divider ratio  (K3DIV + 1)